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vhdlverilog
flyingblindonarocketcycle
flyingblindonarocketcycle

Reputation: 103

Can a verilog module be instantiated in a VHDL module using entity instantiation?

Is it possible to use VHDL style entity instantiation to include a Verilog module in a VHDL design?

I realize that I can accomplish this if I treat the Verilog module as a component and instantiate the component.

Thanks

Upvotes: 3

Views: 11640

Answers (2)

Craig
Craig

Reputation: 928

Although the answer seemed to be "no" 3 years ago when this was asked, I have found the answer in practice to be "yes you can", but with some caveats. I confirmed this using Mentor ModelSim and Xilinx Vivado.

I don't know if something about the LRM changed or if the tool vendors just decided to support it anyway. I'm using VHDL-2008, so I suspect the latter.

Here's an instance I have in one of my test files. VerFlopX is a Verilog module.

  VerFlopX8c: entity work.VerFlopX (rtl)
    generic map (SIZE => 8)  --integer:=1
    port map (
      Clk => Clk,                --in  wire
      D   => D16(15 downto 8) ,  --in  wire[(SIZE-1):0]
      Q   => Q16(15 downto 8));  --out wire[(SIZE-1):0]

The caveats:

  • Note that architecture "rtl" is specified. This can (and probably should) be omitted. But it still works, which seems weird since Verilog modules don't have architectures.
  • You cannot associate the Q output with open. ModelSim will return an error. If you change to a component instantiation, having a formal output connected to open is fine.

Upvotes: 0

Oldfart
Oldfart

Reputation: 6269

Grab from my collection of code:

module sync_fifo
#(parameter WIDTH    = 8, // width in bits
            L2DEPTH  = 4, // Log 2 Depth, 4=16 deep
            REGFLAGS = 1  // Full, empty are registered
)
(
   input                   clk,     // system clock                 
   input                   reset_n, // A-synchronous low reset/clear
   input                   enable,  // clock gating                 
   input                   clear,   // Synchronous clear            

   input                   write,   // write FIFO                   
   input       [WIDTH-1:0] wdata,   // write data                   
   input                   read,    // read FIFO                    
   output      [WIDTH-1:0] rdata,   // read data                    

   output reg              empty,   // FIFO is empty                
   output reg              full,    // FIFO is full                 
   output reg      [L2DEPTH:0] level    // Fill level                   
);

outp_fifo : sync_fifo 
generic map(
   WIDTH   => 10,  -- Byte + user + last
   L2DEPTH => 7,   -- 128 deep
   REGFLAGS=> 1
  )
port map 
(
   clk     => ACLK,                  -- system clock                 
   reset_n => ARESETN,               -- A-synchronous low reset/clear
   enable  => BIT_1 ,                -- clock gating                 
   clear   => BIT_0 ,                -- Synchronous clear            

   write   => package_byte_en,       -- write FIFO                   
   wdata   => outp_fifo_wt_data_and_meta , -- write data                   
   read    => outp_fifo_read   ,     -- read FIFO                    
   rdata   => outp_fifo_rd_data_and_meta ,     -- read data                    
   empty   => outp_fifo_empty,       -- FIFO is empty                
   full    => outp_fifo_full,        -- FIFO is full                 
   level   => open                   -- Fill level      
   );

Post edit:
And you can only do that with a competent declaration:

COMPONENT sync_fifo IS
  generic(
     WIDTH    : integer := 8;
     L2DEPTH  : integer := 8;
     REGFLAGS : integer := 1
  );
  PORT (
       clk    : in STD_LOGIC;         -- system clock                 
       reset_n: in STD_LOGIC;         -- A-synchronous low reset/clear
       enable : in STD_LOGIC;         -- clock gating                 
       clear  : in STD_LOGIC;         -- Synchronous clear            

       write  : in  STD_LOGIC;        -- write FIFO                   
       wdata  : in  STD_LOGIC_VECTOR(WIDTH-1 downto 0); -- write data                   
       read   : in  STD_LOGIC;        -- read FIFO                    
       rdata  : out STD_LOGIC_VECTOR(WIDTH-1 downto 0); -- read data                    

       empty  : out STD_LOGIC; -- FIFO is empty                
       full   : out STD_LOGIC; -- FIFO is full                 
       level   : out STD_LOGIC_VECTOR(L2DEPTH downto 0)  -- Fill level                   
    );
END COMPONENT;

Upvotes: 1

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