CODEWITHSUNDEEP
arraysstringvhdl
nima moradi
nima moradi

Reputation: 2628

can't convert string[] to string in vhdl

i am writing a code in vhdl and bump into this error

 Assignment target incompatible with right side. Cannot convert 'dataArray' to 'STRING'

here is my code

 entity instructionTranslator is
    port(clk :in std_logic;
    instructionCode :in std_logic_vector(4 downto 0);
    instructionType:out std_logic_vector(1 downto 0) ;
    data :out string (1 to 1)--here is data
    );  
end instructionTranslator;
               .
               .
               .
architecture  Translator of instructionTranslator is    
    type dataArray is array (0 to 13)of string(1 to 1);

    process(clk) begin
      data<=dataArray(1);

how should chooses special index of array in vhdl.

Upvotes: 1

Views: 324

Answers (1)

user1818839
user1818839

Reputation:

Here. I made it into an [MCVE] for you. This one compiles.

You declared a type dataArray. You didn't then go on to declare a signal (or variable or constant) of that type.

Assigning a member of a type (which is something abstract) to a real signal obviously won't work.

Assigning a member of a signal (etc) of that type, however, ...

library ieee;
use ieee.std_logic_1164.all;

entity instructionTranslator is
    port(clk :in std_logic;
    instructionCode :in std_logic_vector(4 downto 0);
    instructionType:out std_logic_vector(1 downto 0) ;
    data :out string (1 to 1)--here is data
    );  
end instructionTranslator;


architecture  Translator of instructionTranslator is    
    type dataArray is array (0 to 13)of string(1 to 1);
    signal da : dataArray;
begin

    process(clk) is
    begin
      data<=da(1);
    end process;
end Translator;

Upvotes: 5

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