CODEWITHSUNDEEP
verilogsystem-verilog
Arteezy
Arteezy

Reputation: 333

Using the struct datatype in module in systemverilog

I need to use a struct datatype in the module in SystemVerilog. Some members of the struct contain an array. I get the error "incompatible complex type assignment". I have the following structs contained in common.sv:

typedef struct {
     logic[1:0] num;
     logic val;
   } lit;

typedef lit lit_array[1:0];

typedef struct {
    lit_array lits;
    logic[1:0] len;
   } clause;

typedef clause clause_array[2:0];

typedef struct {
     clause_array clauses;
     logic[2:0] len;
   } formula;

typedef formula formula_array[4:0];

When I try to use the "formula" datatype in module as below, I get the "incompatible complex type assignment" error. The following is the code.

`include "common.sv"
module propagateliteral(input logic clock, reset, find, 
                        input lit in_lit, 
                        input formula in_formula, 
                        output logic ended, empty_clause, empty_formula);
//my system-verilog code

The testbench code:

`include "common.sv"
module pl_test();
logic clock, reset, find;
lit in_lit;
formula in_formula;
logic ended, empty_clause, empty_formula;

propagateliteral test1(clock, reset, find, in_lit, in_formula, ended, 
                       empty_clause, empty_formula);
always
begin
clock=1'b1; #50; clock=1'b0; #50;
end

initial
begin
reset=1'b1; find=1'b0;
#160;
reset=1'b0; find=1'b0;
#100;
reset=1'b0; find=1'b1; in_lit='{2'b01,1'b1};
in_formula='{{{{{2'b01,1'b1},{2'b10,1'b1},{2'b00,1'b1}},2'b10}, //clause0
        {{{2'b10,1'b1},{2'b11,1'b1},{2'b00,1'b1}},2'b10}, //clause1
        {{{2'b01,1'b1},{2'b10,1'b1},{2'b11,1'b1}},2'b11}, //clause2
        {{{2'b01,1'b0},{2'b10,1'b1},{2'b11,1'b0}},2'b11}, //clause3
        {{{2'b01,1'b0},{2'b10,1'b1},{2'b11,1'b0}},2'b11}, //clause4
        {{{2'b01,1'b0},{2'b10,1'b1},{2'b11,1'b0}},2'b11}, //clause5
        {{{2'b01,1'b0},{2'b10,1'b1},{2'b11,1'b0}},2'b11}},3'b100}; //clause6
end
endmodule

After I did some searching, I found that I can not pass unpacked struct datatype. Is there a better way to redefine those structs so that I can use them in the module. Sorry, I'm a newbie to SystemVerilog and I may have not used the correct technical terms in describing my problem. Any help is appreciated.

Upvotes: 2

Views: 2410

Answers (1)

dave_59
dave_59

Reputation: 42788

You need to make sure the struct definition comes from the same package, then repeatedly import the same package for each module. See http://go.mentor.com/package-import-versus-include

Upvotes: 2

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