CODEWITHSUNDEEP
hdlnand2tetris
Mark Alexa
Mark Alexa

Reputation: 125

Implementation of an AND chip in HDL

I'm working through this book http://nand2tetris.org/book.php that teaches fundamental concepts of CS and I got stuck where I'm asked to code an AND chip and test it in provided testing software.

This is what I've got so far:

 /**
 * And gate: 
 * out = 1 if (a == 1 and b == 1)
 *       0 otherwise
 */

CHIP And {
    IN a, b;
    OUT out;

    PARTS:
    // Put your code here:
    Not(in=a, out=nota);
    Not(in=b, out=notb);
    And(a=a, b=b, out=out);
    Or(a=nota, b=b, out=nota);
    Or(a=a, b=notb, out=notb);

}

Problem is I'm getting this error:

...
at Hack.Gates.CompositeGateClass.readParts(Unknown Source)
at Hack.Gates.CompositeGateClass.<init>(Unknown Source)
at Hack.Gates.GateClass.readHDL(Unknown Source)
at Hack.Gates.GateClass.getGateClass(Unknown Source)
at Hack.Gates.CompositeGateClass.readParts(Unknown Source)
at Hack.Gates.CompositeGateClass.<init>(Unknown Source)
at Hack.Gates.GateClass.readHDL(Unknown Source)
...

And I don't know if I'm getting this error because the testing program is malfunctioning or because my code is wrong and the software can't load it up.

Upvotes: 0

Views: 4329

Answers (5)

Steven Mugisha Mizero
Steven Mugisha Mizero

Reputation: 11

This works:

/**
* And gate:
* if (a and b) out = 1, else out = 0 
*/
CHIP And {
     IN a, b;
     OUT out;

     PARTS:
     Nand(a=a, b=b, out=w);
     Not(in=w, out=out);
}

Upvotes: 0

Eddie T
Eddie T

Reputation: 119

I struggled with this, too. I am assuming the comment above about only using NAND gates to make your AND gate is the instruction. Comment "0" above gives us the answer but she didn't "spell it out" for us. (So, it took me a while, still, to find the answer.) For your AND's inputs, a and b, link them to the a and b of a NAND. Then, fan the out of the NAND to the a and b of another NAND. The out of that second NAND can then be mapped to your AND's out.

And this is actually not the only way to do it! This is what makes chip logic so fun!

Upvotes: 0

Antonio Dangond
Antonio Dangond

Reputation: 149

It may be helpful to examine the truth tables for Nand and And:

Nand
a | b | out
0 | 0 | 1
0 | 1 | 1
1 | 0 | 1
1 | 1 | 0

And
a | b | out
0 | 0 | 0
0 | 1 | 0
1 | 0 | 0
1 | 1 | 1

And is the inverse of Nand, meaning that for every combination of inputs, And will give the opposite output of Nand. Another way to think of the "opposite" of a binary value is "not" that value.

If you send 2 inputs through a Nand gate and then send its output through a Not gate, you will have Not(Nand(a, b)), which is equivalent to And(a, b).

Upvotes: 1

Sophie Holtquist
Sophie Holtquist

Reputation: 24

You're overthinking the problem significantly

If one is given NAND, or (not) AND, then AND can be constructed as (not)NAND since (not)(not) AND = AND

Upvotes: 0

Trebor the MadOverlord
Trebor the MadOverlord

Reputation: 1289

Your problem is that you are trying to use parts (Not, And and Or) that haven't been defined yet (and you are trying to use an And gate in your definition of an And gate).

At each point in the course, you can only use parts that you have previously built. If memory serves, at this point the only part you have available is a Nand gate.

You should be able to construct an And gate using only Nand gates.

Upvotes: 0

Related Questions