CODEWITHSUNDEEP
cpu-architecturefpgaintel-fpganand2tetris
Giuseppe Rossini
Giuseppe Rossini

Reputation: 69

How to implement nand2tetris processor on a real FPGA?

I followed the nand2tetris course (https://www.nand2tetris.org/course) with the main intent to learn how to build a soft processor on a real FPGA.

While the course was simple enough, now that I am starting with the FPGA implementation I feel a bit lost.

I bought an Intel de10 nano FPGA(http://de10-nano.terasic.com/), and, having some Verilog knowledge from Uni, I was able to download "Quartus Prime Lite" and bootstrap with simple things like led blinking, etc...

However, when it comes to implement the processor there are several things that are not clear to me:

Those are the main questions I am struggling with at the moment. Could you point me out to any resource useful for a complete novice?

Thanks,

Upvotes: 1

Views: 1665

Answers (2)

user15424993
user15424993

Reputation: 51

I finished implementing the nand2tetris hardware on a small fpga (ice40HX8K) and here are my suggestions:

A. Memory Original nand2tetris uses two memory parts:

  1. ROM for instruction code
  2. RAM for data memory

Both can be implemented using BRAM-cells of fpga. They have the nice property, that BRAM can be preloaded with data at startup. This is useful to preload the ROM with your instruction code. If you have plenty of BRAM you are fine. My board (ice40HX8K-EVB from Olimex) had only 8K x 16bit of BRAM. So I did the following:

  1. I used 512 x 16 bit of BRAM as ROM preloaded with a bootloader (written in Hack-Assembler)
  2. rest of BRAM is used as RAM (7680 x 16 bit)
  3. My board has an external SRAM chip (256 k x 16 bit). I used this as Instruction memory. On startup the bootloader fills the SRAM with Application-code and than "switches" the SRAM to be the instruction memory.

Your board has a separates DRAM-chip. You could use this as Memory too, but be warned: using DRAM is much more tricky than using SRAM.

B. input/output nand2tetris has a screen and a keyboard attached to it.

An easy to implement alternative could be the following: Implement a small UART so you can connect your PC over a terminal (e.g. screen /devttyACM0). Now you can talk to your Hack-CPU (running in fpga) at runtime. I used the UART also to upload Hack-Application at boot time.

Take a look at my repo: https://gitlab.com/x653/nand2tetris-fpga

Upvotes: 5

SK-logic
SK-logic

Reputation: 9715

For something as simple as a CPU from nand2tetris you'll be just ok with block RAMs, there's plenty of it on DE10Nano, likely enough for all your needs. Plus some more distributed memory.

In case if you still want an access to DDR, DE10Nano is an SoC, with a hard DDR controller managed by the processor subsystem. It's very easy to interface with it over an Avalon bus (don't bother with AXI unless you really need maximum possible performance).

For the ROM, just use LUTs. A simple static case in Verilog will be translated into an efficient LUT-based ROM.

For accessing HDMI on DE10Nano, you can take a look at this example: https://github.com/combinatorylogic/soc/blob/a1d282d793548030cba940496bed90ff3a29c0ba/backends/c2/hw/de10nano/vga1080p.v (you can also take a look at the DDR access in the same project). Before you can use HDMI you'll need to set up the ADV7513 chip over i2c, see a copy of a library from Terasic under the same project.

For a monochrome 800x600 video you'll be ok with a block RAM. For higher resolutions, as in the example above, you'll have to use DDR.

Upvotes: 5

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