CODEWITHSUNDEEP
verilog
MinSeob Lim
MinSeob Lim

Reputation: 101

Verilog 2's complement adder/subtraction

design 8-bit adder-subtractor using Verilog.

op=0 --> A+B (add)

op=1 --> A-B (subtract)

i tried to do -87-(-116)=29

I insert testbench #10 A=-8'b10101001; B=-8'b10001100; op=1;

However, Verilog is Negative recognition failed. And Originally result should print 00011101, but result print wrong value 1110 0011

How can i fix this problem?

Below is my code

module addsub8 ( A ,B ,mode ,result ,overflow );

output [7:0] result ;
wire [7:0] result ;
output overflow ;
wire overflow ;

input   [7:0] A ;
wire   [7:0] A ;
input    [7:0] B ;
wire   [7:0] B ;
input mode ;
wire mode ;

//}} End of automatically maintained section

// -- Enter your statements here -- //

wire B0; 
wire B1; 
wire B2; 
wire B3; 
wire B4; 
wire B5; 
wire B6; 
wire B7; 

wire C0; 
wire C1; 
wire C2; 
wire C3;
wire C4; 
wire C5; 
wire C6; 
wire C7;  

xor(B0, B[0], mode);
xor(B1, B[1], mode);
xor(B2, B[2], mode);
xor(B3, B[3], mode);
xor(B4, B[4], mode);
xor(B5, B[5], mode);
xor(B6, B[6], mode);
xor(B7, B[7], mode);


fa U0(A[0],B0,mode,C0,result[0]);
fa U1(A[1],B1,C0,C1,result[1]);
fa U2(A[2],B2,C1,C2,result[2]);
fa U3(A[3],B3,C2,C3,result[3]);
fa U4(A[4],B4,C3,C4,result[4]);
fa U5(A[5],B5,C4,C5,result[5]);
fa U6(A[6],B6,C5,C6,result[6]);
fa U7(A[7],B7,C6,C7,result[7]);  

xor (overflow,C6,C7);                

endmodule


module fa ( A ,B ,Cin ,Cout ,S );

output Cout ;
output  S ;           


input A ;
wire A ;
input B ;
wire B ;
input Cin ;
wire Cin ;    

reg Cout;
reg S;


//}} End of automatically maintained section

// -- Enter your statements here -- //

always @(A or B or Cin) begin
    case ({A,B,Cin})
     0: begin Cout=0; S=0; end
     1: begin Cout=0; S=1; end
     2: begin Cout=0; S=1; end      
     3: begin Cout=1; S=0; end
     4: begin Cout=0; S=1; end
     5: begin Cout=1; S=0; end
     6: begin Cout=1; S=0; end
     7: begin Cout=1; S=1; end
    endcase
    end

endmodule

enter image description here

Upvotes: 0

Views: 13332

Answers (2)

Morgan
Morgan

Reputation: 20514

The code works fine for me in EDA Playground https://www.edaplayground.com/x/5dRL

I guess that your issue is that you check the result immediately and do not allow any time for the result to propagate.

ie 

#10 A=-8'd87; B=8'b116; op=0;
Check answer

allowing at least 1 time step allows a combinatorial answer to propagate:

#10 A=-8'd87; B=8'b116; op=0;
#1;
Check answer

Upvotes: 1

Oldfart
Oldfart

Reputation: 6259

1/ If you wan to work with negative numbers like -A and if you want 8'b10101001 to be seen as a negative number use signed vectors: 

input  signed [7:0] A ;
wire   signed [7:0] A ;

I quickly scanned your code and I see only standard (unsigned) vectors.

2/ Do not mess about with one bit full adders, just use the language:

assign R = A + B;

Upvotes: 1

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