CODEWITHSUNDEEP
veriloghdliverilog
Subhadip
Subhadip

Reputation: 21

4 bit adder-subtractor in verilog

I am writing verilog code for 4 bit adder subtractor. I am using structural design. At first I have written verilog code for 1 bit full adder. Then I am using that to write code for 4 bit adder subtractor .

module fadder (A, B, Cin, Sum, Cout);
    input A, B;
    input Cin;
    output Sum;
    output Cout;
    wire t1,t2,t3,t4;
  xor x1(t1,A,B);
  xor x2(Sum,t1,Cin);
  and g1(t2,A,B);
  and g2(t3,B,Cin);
  and g3(t4,Cin,A);
  or  g4(Cout,t2,t3,t4);  
endmodule


module add_sub_4 (A, B, In, Res, Out);
    input [3:0] A, B;
    input In;
    output [3:0] Res;
    output Out;
    wire t1,t2,t3,t4,t5,t6,t7;


          xor x3(t3,B[0],In);
          xor x4(t4,B[1],In);
          xor x5(t5,B[2],In);
          xor x6(t6,B[3],In);
          fadder f5(A[0],t3,In,Res[0],t1);
          fadder f6(A[1],t4,t1,Res[1],t2);
          fadder f7(A[2],t5,t2,Res[2],t3);
          fadder f8(A[3],t6,t3,Res[3],Out);  
endmodule

Upvotes: 1

Views: 43026

Answers (3)

Adarsh Mohapatra
Adarsh Mohapatra

Reputation: 11

The error is because you are using t3 to store the output of an xor operation as well as a full adder operation. I modified the names of the wire variables so that they don't clash and created a testbench. Now it works fine. For subtraction it returns negative numbers as 2's complement of it's corresponding positive value.

module fadder (A, B, Cin, Sum, Cout);
  input A, B;
  input Cin;
  output Sum;
  output Cout;
  wire t1,t2,t3,t4;
  xor x1(t1,A,B);
  xor x2(Sum,t1,Cin);
  and g1(t2,A,B);
  and g2(t3,B,Cin);
  and g3(t4,Cin,A);
  or  g4(Cout,t2,t3,t4);  
endmodule


module add_sub_4 (A, B, In, Res, Out);
    input [3:0] A, B;
    input In;
    output [3:0] Res;
    output Out;
    wire t0,t1,t2,t3,t4,t5,t6;


          xor x3(t0,B[0],In);
          xor x4(t1,B[1],In);
          xor x5(t2,B[2],In);
          xor x6(t3,B[3],In);
          fadder f5(A[0],t0,In,Res[0],t4);
          fadder f6(A[1],t1,t4,Res[1],t5);
          fadder f7(A[2],t2,t5,Res[2],t6);
          fadder f8(A[3],t3,t6,Res[3],Out);  
endmodule

module add_sub_4_tb;
reg [3:0] A,B;
reg In;
wire [3:0] Res;
wire Out;
add_sub_4 tb(A,B,In,Res,Out);
initial
begin
In=0; A=4'b1010; B=4'b0101;
#10 In=1;
#10 In=0; A=4'b0101; B=4'b1010;
#10 In=1;
#10 In=0; A=4'b1111; B=4'b1111;
end 
endmodule

Upvotes: 1

Amritanjan Kumar
Amritanjan Kumar

Reputation: 1

Make use of complimenting B using XOR gate (when in=1) before putting into the values in the instantiated modules.

when the in=0, same B will be added to A and when in=1, ~B will be added to A.

Upvotes: 0

dustinwerran
dustinwerran

Reputation: 26

You're actually pretty close. What you seem to not understand is that in Verilog your design is synthesized at compile time, not at run time. You can't instantiate modules conditionally because at compile time we don't know if that condition will be met or not. So your first statement in the case of the subtraction bit being low doesn't really make sense. It also doesn't make sense to put it in an always block, since the rtl is defined in the modules already.

However, your second statement contains most of the solution to the problem. When the sign bit is low, those xors at the top of the adder/subtractor will preserve the incoming bits, and the design will simplify to just an adder. Try just using the second block alone.

Upvotes: 1

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