CODEWITHSUNDEEP
vhdlfpgatest-bench
Thanh niên Yên Bái
Thanh niên Yên Bái

Reputation: 41

code VHDL one shot timer

Now I'm coding VHDL to make a one-shot timer module. But I don't know which code is right in two kind of code, the first or second. i used the testbench i see the different. What the right code for monostable (one-shot) ?

This is the first code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;

entity oneshot is
port ( clk : in STD_LOGIC;
        ce : in STD_LOGIC;
        trigger : in STD_LOGIC;
        delay : in STD_LOGIC_VECTOR (7 downto 0);
        pulse : out STD_LOGIC :='0');
end oneshot;
architecture Behavioral of oneshot is
signal count: INTEGER range 0 to 255; -- count variable
begin
process (clk,delay,trigger)
begin
-- wait for trigger leading edge
if rising_edge(clk) then 
    if trigger = '1' then
        count <= to_integer(unsigned(delay));   
    end if;
    if count > 0 then
        pulse <= '1';
        count <= count - 1;
    else
        pulse <= '0';
    end if;
end if;
end process;
end Behavioral;

testbench imagine of the first code

This is second one:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;

entity oneshot is
port ( clk : in STD_LOGIC;
        ce : in STD_LOGIC;
        trigger : in STD_LOGIC:='0';
        delay : in STD_LOGIC_VECTOR (7 downto 0);
        pulse : out STD_LOGIC :='0');
end oneshot;
architecture Behavioral of oneshot is
signal count: INTEGER range 0 to 255; -- count variable
begin
process (clk,delay,trigger)
begin
-- wait for trigger leading edge
if trigger = '1' then
count <= to_integer(unsigned(delay));
elsif rising_edge(clk) then
    if count > 0 then
        pulse <= '1';
        count <= count - 1;
    else
        pulse <= '0';
    end if;
end if;
end process;
end Behavioral;

testbench of the second one

Upvotes: 1

Views: 3929

Answers (1)

Paebbels
Paebbels

Reputation: 16221

Both versions cannot be synthesized:

  • The first has code outside the rising_edge condition.
  • The second code has an asynchronous load condition.
    That's not supported by FPGA. That's not supported by all FPGA.

In general the second implementation is the closest to a solution. You can improve the down-counter by counting towards -1 und using the signed type. -1 can be identified by the MSB being '1'. No need to compare n bits for all zero.

Further issues:

  • The sensitivity list is wrong.
    • Signal trigger is missing
    • Signal flag is not read
  • Library unisim is unused.
  • Signal flag is unused.

Upvotes: 2

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