CODEWITHSUNDEEP
verilogsystem-verilog
jkang
jkang

Reputation: 549

Find MAX value of `define in Verilog

I want to create a define constant that is assigned to one of multiple otherdefine constants that has the largest value. Something like:

`define MAXWIDTH $MAX(`WIDTH0,`WIDTH1,`WIDTH2)

Is this possible in Verilog/SystemVerilog?

Upvotes: 1

Views: 4575

Answers (1)

Unn
Unn

Reputation: 5108

Depending on exactly what you need, there are a few ways to do it (there is no builtin call for maximum like in other languages):

You have some vectors and you need to get the maximum width for a new vector

$bits(v1 + v2 + v3 ...)

Use the language to your advantage, noting that the addition of vectors results in a vector that has the maximum width of all the operand vector widths and use $bits to get that size. Example:

logic [1:0] x;
logic [7:0] y;
logic [10:6] z;
...
max = $bits(x + y + z); // Result: max = 8

You have a few numbers of which you need the maximum

If you put your numbers in an array or queue, you can use the max method to get the largest:

int x[] = '{n1, n2, n3, ...};
...
max = x.max;

Note that this approach has the downside that it cannot be used at compile time for getting the maximum size. Example:

int _nums[] = '{13, 2, 17, 8, -1};
...
max = _nums.max; // Result: max = 17

Basically any other time

You'll just have to use the conditional operator, either in a macro or using let:

`define max2(v1, v2) ((v1) > (v2) ? (v1) : (v2))
`define max3(v1, v2, v3) `max2((v1), `max2((v2), (v3)))

OR

let max2(v1, v2) = (v1 > v2) ? v1 : v2;
let max3(v1, v2, v3) = max2(v1, max2(v2, v3));

The advantage of macros is that you can use them as compile-time constants in a wider range of tools, while older tools might not support let as a compile-time constant (or at all). Example:

max = `max3(10, 2, 3); // Result: max = 10

OR

max = max3(10, 2, 3); // Result: max = 10

Upvotes: 5

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