CODEWITHSUNDEEP
verilogsystem-verilog
user3383729
user3383729

Reputation: 27

using assign statement for `define statement

I am using assign statement of verilog for assigning `define as below in my driver module.

`define  SPI_MASTER_P_IF spi_vif.spi_master_p.spi_master_p_cb

`define SPI_MASTER_N_IF spi_vif.spi_master_n.spi_master_n_cb

`define SPI_MASTER_IF

class my_driver extends uvm_driver;

  assign `SPI_MASTER_IF = (if_posedge)?`SPI_MASTER_P_IF: `SPI_MASTER_N_IF;

endclass

When I compile I am facing the error as "near "assign": syntax error, unexpected assign, expecting function or task"

What is the proper way to do this assignment?

Upvotes: 1

Views: 1363

Answers (2)

nguthrie
nguthrie

Reputation: 2685

You cannot define a macro using an assign statement. What you want here is ifdef:

`ifdef IF_POSEDGE
  `define SPI_MASTER_IF SPI_MASTER_P_IF
`else
  `define SPI_MASTER_IF SPI_MASTER_N_IF
`endif

See section 22.6 of the 1800-2012 standard.

Upvotes: 4

Sung-Yu Chen
Sung-Yu Chen

Reputation: 31

The definition SPI_MASTER_IF is empty. The code becomes:

assign = (if_posedge)?spi_vif.spi_master_p.spi_master_p_cb:spi_vif.spi_master_n.spi_master_n_cb

which is illegal.

Also assign might not be used there too, please check the IEEE Std 1800-2012 section 8.3 (class syntax) in the specification.

Upvotes: 3

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