CODEWITHSUNDEEP
verilog
user3188828
user3188828

Reputation: 31

In synthesizable verilog, can we use assign statement in generate block?

For example, I have the below piece of code. Can we assign wire inside the generate block in synthesizable verilog? Can we use assign statement inside the generate block in synthesizable verilog? 

genvar i;
generate
        for (i = 0; i < W; i=i+1) begin:m
                wire [2:0] L;
                assign L[1:0] = { a[i], b[i] };
        end
endgenerate

Upvotes: 2

Views: 34345

Answers (3)

Morgan
Morgan

Reputation: 20544

You can use assign in generate statment, it is quite common to help parameterise the hook up modules

The original code has some issues: L is defined multiple times and it is only assigned 2 out of 3 bits

genvar i;
generate
  for (i = 0; i < W; i=i+1) begin:m
    wire [2:0] L;
    assign L[1:0] = { a[i], b[i] };
  end
endgenerate

Could be changed to:

localparam   W = 4;
reg  [W-1:0] a;
reg  [W-1:0] b;
wire   [1:0] L [0:W-1];

genvar i;
generate
  for (i = 0; i < W; i=i+1) begin:m
    assign L[i] = { a[i], b[i] };
  end
endgenerate

Here L[i] selects the i'th wire [1:0] part of L. While a[i] and b[i] are bit selects.

Upvotes: 0

Akaberto
Akaberto

Reputation: 433

Yes. It is possible. A generate statement is just a code generator directive to the synthesizer. Basically, it is just loop unrolling. This is if the loop can be statically elaborated. That is, the number of times the loop is to executed should be determinable at compile time.

genvar i;        
generate        
for (i = 0; i < 2 ; i++) {        
  assign x[i] = i;}        
endgenerate 

unrolls into         
assign x[0] = 0;        
assign x[1] = 1;

Upvotes: 4

ngwilliams
ngwilliams

Reputation: 269

In synthesizeable Verilog, it is possible to use an assign statement inside of a generate block. All a generate block does is mimic multiple instants. Be careful though, because just like a for loop, it could be very big space-wise.

Upvotes: 0

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