CODEWITHSUNDEEP
verilogsystem-verilog
gnoejh
gnoejh

Reputation: 335

How to represent assign logic array in Verilog generate block?

I have difficulties in representing a simple assignment with generate block. My intention is assign bus = disp[0] | disp[1] | disp[2] ...; The following code does not work. How can I fix it? Such accumulation related assignments does not appear in the Verilog mannual. Thanks in advance for any advice.

genvar varx;
for (varx = 0; varx < `N; varx = varx + 1) begin
    if (varx == 0) assign bus = disp[0];
    else assign bus = bus | disp[varx];
    end

Upvotes: 1

Views: 4765

Answers (1)

Morgan
Morgan

Reputation: 20514

That is an incorrect usage of generate and assign.

generates should not be used that liberally in Verilog and their use should be something special like extending a module for parametrization etc.

If it can be statically unrolled (as per your usage here) then a plain for loop could have been used. Generates would typically be used for parametrizing module instantiations;

assign should be once per wire and constantly drives the right hand side expression on to that wire.

Your code looks like you are simply trying to OR the disp bus, this can be achieved with an OR reduction operator:

wire bus;
assign bus = |disp ;

Update1

disp is actually defined as a memory and we are not trying to calculate a single bit or reduction. Here a for loop can be used to calculate the OR.

logic [3:0] data [5:0];
logic [3:0] or_data;
integer i;

always @* begin
  or_data = 4'b0; 
  for(i=0; i<6; i=i+1) begin
    or_data = or_data | data[i] ;
  end
end

Simple Simulation:

logic [3:0] data [5:0];
logic [3:0] or_data;
integer i;
initial begin
  for(i=0; i<6; i=i+1) begin
    data[i] = i*2;
  end
  #1ns;
  for(i=0; i<6; i=i+1) begin
    $displayb(data[i]);
  end

  or_data = 4'b0; 
  for(i=0; i<6; i=i+1) begin
    or_data = or_data | data[i] ;
  end
  #1ns;
  $displayb(or_data);
end

Upvotes: 3

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