CODEWITHSUNDEEP
verilogsystem-verilog
Misal313
Misal313

Reputation: 179

Generate Statement in verilog for multiple Blocks

In the code you can see that, I want to instantiate LSFR_counter for 8 times using generate statement. It simulated well, but I want to synthesize for FPGA.

I have problems which are:

1) I found an error when synthesized it. 

Line 31: Signal Reg[4] in unit Main is connected to following multiple drivers:

2) Can I use random parameter for #(.n(random))?

module Main( output Reg , input clk , input reset );     

 parameter N =5 ;
 wire  [N-1:0] Reg ; 
 generate    
   genvar i =0 ;
   for (i ; i<8 ; i=i+1 )
   begin 
   LSFR_counter   #(.n(5)) F1  ( .Reg (Reg )  , .clk (clk ), .reset(reset) );  
   end 
 endgenerate 
endmodule

and 

    module LSFR_counter  #(parameter n=6)( output Reg, input clk, input reset);
    //parameter n=6; // Change more than n to change LFSR length.

    reg [n:1]Reg; //All procedure outputs must be registered

    always @(posedge clk or posedge reset)
        if
        (reset) Reg <=1;
        else
        Reg <= {Reg[n-1:2], Reg[n]^Reg[1], Reg[n]};
    endmodule

Upvotes: 0

Views: 1843

Answers (1)

Morgan
Morgan

Reputation: 20564

Multiple divers means that you have multiple modules trying to set the value of Reg. As a side note I really would advise to use some thing else other than Reg as a signal name, not least because at the top level it is a wire.

Thinking about your generate around the LFSR it would unroll to something like:

LSFR_counter   #(.n(5)) F1_1  ( .Reg (Reg )  , .clk (clk ), .reset(reset) );
LSFR_counter   #(.n(5)) F1_2  ( .Reg (Reg )  , .clk (clk ), .reset(reset) );
LSFR_counter   #(.n(5)) F1_3  ( .Reg (Reg )  , .clk (clk ), .reset(reset) );

clk and reset are inputs and they can drive multiple modules, but reg is an output which all of them are trying to drive.

In simulation you may not see an issue as you have multiple modules all driving the exact same value.

You likely wanted some thing along the lines of:

wire  [N-1:0] Reg [0:7]; //<-- memory
genvar i =0 ;   
generate    
  for (i ; i<8 ; i=i+1 ) begin 
    LSFR_counter #(
     .n(5)
    ) F1  ( 
     .Reg  (Reg[i]  ), //<-- write to part of memory
     .clk  (clk  ),
     .reset(reset) 
    );  
  end 
endgenerate

Upvotes: 2

Related Questions