CODEWITHSUNDEEP
verilog
Prashant Vaidyanathan
Prashant Vaidyanathan

Reputation: 488

Using an if else condition in a generate block in Verilog

I have a code where I am using recursion, 

module mult(a,b,c)
  generate
    always @(*) begin
     /* a few calculations */
     if(x < 10)
       flag = 1;
     else
       flag = 0; 
    end
     if( flag == 1)
        mult(x,y,z);
     else
        z = x*y;
  endgenerate
endmodule

However, this code returns an error saying that flag is not a constant. I understand that one cannot use an if-else outside the always block, by using registers or wires or integers. However, is there any other way I can implement the code?

Recursion seems to work only in a generate block but outside the always block.

Upvotes: 0

Views: 2900

Answers (1)

Brian Magnuson
Brian Magnuson

Reputation: 1487

Conditionals in generate blocks need to be constant at elaboration time. Typically they either `defines or parameters of the module.

You don't declare 'x' at all in your example... In fact there are numerous errors that would prevent this from compiling. Enough that it's hard to figure our your intent. Can you provide a bit of detail on this?

Upvotes: 1

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