CODEWITHSUNDEEP
verilog
toozie21
toozie21

Reputation: 341

Is there a way to do nested generate statements in Verilog?

I am trying to reduce some code by using generate statements, but I can only figure out how to do via nesting, but I don't believe that that is allowed.

What I have is essentially some for-loops running (which require a generate), and within them I want to run one of three sections of code depending on a value that is set when the code is built (which then requires a second generate). Is there a way to do this and make the tools happy?

Here is a quick-and-dirt picture of what I am trying:

    //TAPS_PER_CHAN is a value defined when the code is built
genvar srcNode, dstNode, tapIdx;
 generate
  for (dstNode=0; dstNode<NODES; dstNode=dstNode+1)
    begin: dstForLoop
    generate
        if(TAPS_PER_CHAN <= 4)
        begin
            call module one
        end    
        else if (TAPS_PER_CHAN <= 8)
        begin
            call module two
        end      
       else if (TAPS_PER_CHAN <= 16)
       begin  
            call module three
        end
    endgenerate
    end
endgenerate

Upvotes: 5

Views: 23800

Answers (2)

Greg
Greg

Reputation: 19094

Yes, simply remove then nested generate/endgenerate keywords.
See IEEE Std 1800-2012 § 27 Generate constructs. 

    //TAPS_PER_CHAN is a value defined when the code is built
genvar srcNode, dstNode, tapIdx;
 generate
  for (dstNode=0; dstNode<NODES; dstNode=dstNode+1)
    begin: dstForLoop
    // generate <-- remove this
        if(TAPS_PER_CHAN <= 4)
        begin
            call module one
        end    
        else if (TAPS_PER_CHAN <= 8)
        begin
            call module two
        end      
       else if (TAPS_PER_CHAN <= 16)
       begin  
            call module three
        end
    // endgenerate <-- remove this
    end
endgenerate

example here

Upvotes: 5

archiewu
archiewu

Reputation: 1

Once is in Generate block, Verilog compiler/simulator automatic identify variable (if-else, for-loop) vs Parameter+gen_var(if-else, for-loop) So, if you define TAP_PER_CHAN as parameter, you don't need second generate, and verilog/simulator will generate only one of three modules:

It works and identify correct construct in my NC-Verilog, Ascent-Lint, and Novas-nTrace.

parameter TAP_PER_CHAN; genvar srcNode, dstNode, tapIdx; generate for (dstNode=0; dstNode else if (TAPS_PER_CHAN <= 8) begin call module two end
else if (TAPS_PER_CHAN <= 16) begin
call module three end // endgenerate <-- remove this end endgenerate

Upvotes: 0

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