CODEWITHSUNDEEP
for-loopverilog
Nandhini
Nandhini

Reputation: 61

generate statement : verilog

I need to declare a register inside a generate statement to store some temporary values,

to be used in instantiations.

i have 

generate

for(i=0; i< N; i=i+1)
begin: i_loop
    Inst_file u(S1(i),P1(i),S(i),P(i)); 
    /* S1 and P1 have N bits and 
       S = S1 ^ P1; 
       P = S1 & P1 
     */
end //i_loop

S1 and P1 are simple combinationl logic and i have used them as wires for the first

iteration. But after each iteration of i, I need to assign the outputs S and P as inputs

(i.e replace S1 and P1 with S and P).

I understand I should do it with a register and not a wire (Am i right?)

In such a case i need S1 and P1 as reg. I tried using always statement inside the

generate. It gives error.

Can u please suggest a way out..

Upvotes: 0

Views: 11825

Answers (1)

virtuallinux
virtuallinux

Reputation: 1016

You should use an N+1 bit wide bus, and pull all initialization outside of the generate block. I believe something like this will do:

wire [N:0]Sarray;
wire [N:0]Parray;

// initialize Sarray[0] and Parray[0] here using continuous assignment

generate
for(i=0; i< N; i=i+1)
begin: i_loop

    Inst_file u(Sarray[i],Parray[i],Sarray[i+1],Parray[i+1]);

end //i_loop

Sarray[0] and Parray[0] should be initialized for use in the first iteration; Sarray[N] and Parray[N] will be the final output value of the chain of modules.

Upvotes: 2

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