CODEWITHSUNDEEP
vhdl
TRoa
TRoa

Reputation: 354

Accessing array elements using std_logic_vector (VHDL)

Please see the code below:

....
port(
the_input: in std_logic_vector(0 to 3));
...
type dummy_array is array (0 to 2) of std_logic_vector (0 to 7);
signal ins_dummy: dummy_array := ( 8x"1",  8x"2", 8x"3");
...

Now I want to access the elements of this array using bits the_input(0 to 1). How can I do this? as I know array accepts integers as arguments, but this input is std_logic. I tried many solution available on different forums but nothing seems to be working. For example when I apply this: to_integer(unsigned(the_input(0 to 1))), result is zero.

What is happening? I don't know. Any suggestions?

Upvotes: 5

Views: 7326

Answers (1)

F Gonc
F Gonc

Reputation: 21

Using the small testbench below, I was able to access elements of the array using the method you mentioned -> some_array(to_integer(unsigned(some_signal))).

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;   
use std.textio.all;
use ieee.std_logic_textio.all;

entity test is
end entity test;

architecture behav of test is
    signal the_input : std_logic_vector(0 to 3);
    signal test_sig  : std_logic_vector(7 downto 0);
    type dummy_array is array(0 to 2) of std_logic_vector(7 downto 0);
    signal ins_dummy : dummy_array := (x"01", x"02", x"03");

begin

    test_sig <= ins_dummy(to_integer(unsigned(the_input)));

    process
    begin
    wait for 1 ns;
    the_input <= "0000";
    wait for 1 ns;
    the_input <= "0001";
    wait for 1 ns;
    the_input <= "0010";
    end process;
end architecture behav;

However, this is a simulation and a synthesizer may complain because the range of the port the_input is larger than the number of possible array options. You might have to add logic to ensure that the array indices which are "out of bounds" cannot be accessed. Hope that helps. Possibly try:

test_sig <= ins_dummy(to_integer(unsigned(the_input))) when (the_input < 3) else
            others => '0';

Upvotes: 2

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