Reputation: 23
I understand the difference between structural and behavioural verilog. I am just wondering if you can use both of them within the same module? Or is it bad practice and suggested to stick to one at a time?
Upvotes: 0
Views: 689
Reputation: 42698
One of the breakthroughs Verilog made in the 1980's was bridging structural and behavioral constructs into a single language. So the direct answer to you question is; yes, it was designed that way. What makes a good practice is a matter of opinion, and that's not a topic for stack exchange.
Upvotes: 1