CODEWITHSUNDEEP
system-verilog
DarinT
DarinT

Reputation: 5

SystemVerilog Interface data type with list of instance names

be_nl_i and xbc_i are interface modules. Code example A with a list of instance names compiles.

Example A

be_nl_i be_nl0 (), be_nl1 ();

However, example B with another interface data type does not compile.

Example B

xbc_i #(.NUM(3)) xbc0 (clk), #(.NUM(3)) xbc0_d1 (clk), #(.NUM(3)) xbc0_d2 (clk);

Is there a proper syntax to compile example B?

Upvotes: 0

Views: 99

Answers (2)

refaelga
refaelga

Reputation: 1

Looks like the single line declaration doesn't go well with modules/interface. Following code should work.

    xbc_i #(.NUM(3)) xbc0 (clk);
    xbc_i #(.NUM(3)) xbc0_d1 (clk); 
    xbc_i #(.NUM(3)) xbc0_d2 (clk);

Upvotes: 0

dave_59
dave_59

Reputation: 42788

Parameter overrides of a module is not instance specific. 

xbc_i #(.NUM(3)) xbc0 (clk), xbc0_d1 (clk),  xbc0_d2 (clk);

Upvotes: 2

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