CODEWITHSUNDEEP
arraysverilogsynthesis
user2996871
user2996871

Reputation: 19

Vivado giving issues when trying to slice an array using non-constant integer

I'm using Verilog for a design and am using an integer that gets re-defined every time the always block runs at the positive clock edge. This works fine for one of my two arrays in the always block, but Vivado complains about (only) the second array that uses a "non-constant" for the index for selecting a slice of the array. o_pl_inst is a 128-bit register, and csh_reg is a 128-megabit register, of which I'm selecting 128 bits at a time to store in o_pl_inst. How is it that in the same situation, I'm having no issues with assigning to a dynamic slice of an array, as in "csh_reg[i*i-127] = activ_inst;" but I can't get a value in the same manor? Any assistance would be greatly appreciated.

I've tried moving my array declarations to outside of the always block, but that caused new issues.

    always@(posedge clk) begin
            // Load instructions into the CSH
            int i = (inst_width*(sp_csh+1))-1; /*Reference index generation for dynamic array slicing*/
            int j = (i_pl_sp*128)-1; /*Reference index generation for dynamic array slicing*/

            csh_reg[i*i-127] = activ_inst; /*Load 128-bit instructions into the array 128 bits apart*/
            sp_csh = sp_csh +1; /*Increment internal CSH_sp*/
            activ_inst = i_ps_inst; /*Get next instruction*/

            // Save instruction from CSH
            o_pl_inst = csh_reg[j:j-127]; /*Retrieve 128-bit instruction from 1 of 1048576 positions in CSH*/
    end

I need the fix/alternative to be synthesizable. From what I've read, Vivado tends to have issues with using a non-constant be using to slice an array, but it's only happened with the second array...

Upvotes: 0

Views: 772

Answers (1)

user2996871
user2996871

Reputation: 19

The issue has been resolved thanks largely to the comments. I will share what was changed to get it to function; First, my BRAM usage was too high. Obviously before attempting synthesis I wasn't getting any warnings about that, but I would've run into it either during synthesis or implementation, so I adjusted that in accordance with my chip's datasheet to not use more than the available BRAM. Second, I was using a form of dynamic slicing that wasn't supported in Vivado, but was supported in other tools such as Quartus, so I changed that using the link shared in the comment by @dwikle. After that I was left with an error that was just a silly mistake on my part in my declaration: I had declared one of my parameters as a vector, and tried to assign it to an array. So I changed that. Thanks everyone.

Upvotes: 1

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