CODEWITHSUNDEEP
verilogsystem-verilog
Dhaneshwar Surya
Dhaneshwar Surya

Reputation: 9

problem during initiation of a module in another module

i'm getting an error in the exp function instantiation in the activation module. I'm not able to understand the error in the code. have i done a mistake with respect to the instantiation?

please help me find out!

code - 

module exp (input [15:0] g, output [15:0] f);
real base = 2.71828;
assign f = $realtobits(base ** g) ;
endmodule

module activation(input method,
input ctrl,
input [15:0] imgin[127:0],
output reg [15:0] imgo[127:0]
);

`define ONE 16'h0100;

reg [15:0] y; 

integer i;
always@(ctrl)
for(i=0; i<128 ; i=i+1)
begin 

if(method == 1'b0)   begin  // for relu unit 
if (imgin[i][15])
imgo[i] = 16'h0000;

else if(imgin[i] > 16'b0)
imgo[i]= imgin[i];

else if(imgin[i]>16'b1)
imgo[i]=16'd1;

end

if(method == 1'b1)   begin  // for sigmoid function
  exp f1(.g(imgin[i]),.f(y));   // error here
  imgo[i] = 1/(1+ y);

end
end


endmodule

Upvotes: 0

Views: 86

Answers (1)

Silicon1602
Silicon1602

Reputation: 1181

Edit: Initially I tried to answer the question by also giving solution with uses a module and only suggested to use a function. However, as Greg pointed out in a comment to this answer, a function is the way to go. Therefore, I removed the attempt to answer this question by using a module.

What you are trying to do is to instantiate a module under a certain condition. This is not possible the way you are trying to do this. As described in section 27 of the IEEE Std 1800-2012. ("the Verilog manual"), you can use generate constructs to conditionally instantiate modules. This looks generally like this:

generate
  if (SOME_CONDITION)
     // Instantiate a module
  else
     // Instantiate another module or do nothing
endgenerate

However, in your case, this is not necessary. Instead, you should use a function for this. Section 13.4 of the aforementioned manual points out how to use functions and also this tutorial of nandland.com. You can condintionally call functions. Basically, your code would look like this with a function:

module activation(input             method,
                  input             ctrl,
                  input      [15:0] imgin   [127:0],
                  output reg [15:0] imgo    [127:0]);

  function exp;
    input [15:0] g;
    real         base;

    begin
      base = 2.71828;
      exp  = $realtobits(base ** g);
    end
  endfunction

  `define ONE 16'h0100;

  reg [15:0] y;

  integer i;
  always@(ctrl)
    for(i=0; i<128 ; i=i+1)
    begin

    if(method == 1'b0)   begin  // for relu unit 
      if (imgin[i][15])
        imgo[i] = 16'h0000;
      else if(imgin[i] > 16'b0)
        imgo[i]= imgin[i];
      else if(imgin[i]>16'b1)
        imgo[i]=16'd1;
    end
    else if (method == 1'b1) begin  // for sigmoid function
       y = exp(imgin[i]);
       imgo[i] = 1/(1+ y);
    end
  end
endmodule

Upvotes: 2

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