Data Valid signal in Verilog

Question

I am trying to implement data_valid signal in one of my modules. So far I thought of a solution using counter. Also when I have a valid input I will turn on the enable pin to start processing data.

The module I implemented requires 5 clock cycles to produce the valid output data. The idea is to count till 5 clock cycles and after that setting the valid signal to high and then resetting the counter after providing the valid data.

Following is a short sample version what I want to do where I get the valid data after 1 cycle. But obviously it is not working perfectly and I can't exactly point out where am I missing something.

Example code:

module control_unit (  
        input   [3:0] a,
        input   [3:0] b,            
        input   [3:0] m,            
        input         clk, 
        input         enable, 
        input         nreset,
        output        data_valid, 
        output  [7:0] o
);

        reg [7:0] r1;
        reg [4:0] c;
        reg  count;

        always @(posedge clk or negedge nreset)
            begin
            if (~nreset) count <= 1'b0;
            else if (enable)            
                count <= count+1'b1;
            else count = count;
            end

        assign data_valid = (count == 1'b1) ? 1'b1 : 1'b0;


        always @(posedge clk)
            begin
                c <= a+b;
                r1 <= c[3:0]*m;
            end     

        assign o = r1;

endmodule

Test bench code:

`timescale 1ns/10ps
module tb_control_unit (
                    );


 reg clk;
 reg enable;
 reg nreset;
 wire data_valid;
 reg[3:0] a,b,m;
 wire [7:0] o;

 control_unit control_unit_i (
            .clk(clk),
            .enable(enable),
            .nreset(nreset),
            .data_valid(data_valid),
            .a(a),
            .b(b),
            .m(m),
            .o(o)
                  );


 parameter CLKPERIODE = 10;

 initial clk = 1'b1;
 always #(CLKPERIODE/2) clk = !clk;
 initial enable = 1'b1;

 initial begin

 a = 4'b0001;
 b = 4'b0001;
 m = 4'b0010;

#10 nreset =1'b0;
//#20 nreset =1'b1;

#20 a = 4'b0010;
 b = 4'b0010;
 m = 4'b0001;

#100 $finish();
end

endmodule

Please note: The current state of the code represents a version of my many trials based on my beginner skills.

The problem I am facing is that, the data_valid signal is not providing any output properly in the first few clock cycles and my counter is out of sync due to that (Probably the assign statement is one of many reasons?)

To sum it up,

valid_input arrives then ==> enable=1,
Clock cycle count and calculation starts in parallel,
After 5th clock cycle: final calculation done, data_valid=1,
Counter resets,data_valid=0, waiting for next valid input and enable=1.

Questions:

Is there anything wrong with my concept? How can I maintain the proper counting from the very beginning depending on my control signals?

Please keep in mind, end of the day I will do synthesis and the condition of my project is to use least area.

So, what will be the best way to implement the condition: "if count==5", "data_valid <=1'b1"?

Data Valid signal in Verilog

Answers (1)

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