CODEWITHSUNDEEP
xilinxvivadozynq
CJC
CJC

Reputation: 817

Xilinx Vivado: Block Design, Address Range of each module end point

Consider a design where the PS (Zynq ARM A9) is connected to multiple peripherals where the addressing is depicted below.

Block Design: Address Editor

As highlighted in the purple below, why is the minimum accessible of each endpoint module (even if the module is my own IP) always at a range of four kilobytes? Is it related to something ARM processor specific?

I have tried to modify the address range of my own IP as shown below to a smaller number but it never has any effect.

IP Packaging: Addressing and Memory

Upvotes: 1

Views: 2937

Answers (2)

CJC
CJC

Reputation: 817

In addition to the answer posted by TWang, I want to also note that a user's ability to assign address range depends on the starting address such that the end address will not cross over (or in another words, no carry over) to the next bit.

As can be seen, if you assign the offset address as 0x40020000, you can set the range to be 128K, which mean 0x40020000 to 0x4003FFFF.

I suppose this is a way to manage the memory so that no crazy behaviors can occur.

I am not sure if this is a design intention of Xilinx or a specification of ARM processor architecture.

Addressmap

Upvotes: 0

twang
twang

Reputation: 66

According to notes under Table 3-9: AXI Crossbar Master Interface-Related Parameters in PG059 AXI Interconnect Product Guide, the size of all address range must be a power of 2, determined by 2 ** Mmm_Aaa_ADDR_WIDTH.

Since the master of AXI-Interconnect in your design is probably connected to the AXI4 GP Slave interface of PS system, the Mmm_Aaa_BASE_ADDR is greater than or equal to 12, i.e. the minimum address range that can be assigned to each IP core is at least 4KBytes (4096) as shown in your pictures.

From a design perspective, if you do not run out of memory space to allocate for your IP cores, a bigger range may be better as it reduces the bits needed for comparison in the AXI interconnect, resulting in lower hardware resource consumption, and possibly improved speed (faster achievable AXI clock) and easier placement and routing with timing constraints.

Upvotes: 2

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