CODEWITHSUNDEEP
veriloghdl
Galiei
Galiei

Reputation: 1

a problem on HDLBits: Design a 1-12 counter with the following inputs and outputs

Design a 1-12 counter with the following inputs and outputs:

Reset Synchronous active-high reset that forces the counter to 1 Enable Set high for the counter to run Clk Positive edge-triggered clock input Q[3:0] The output of the counter c_enable, c_load, c_d[3:0] Control signals going to the provided 4-bit counter, so correct operation can be verified. You have the following components available:

the 4-bit binary counter (count4) below, which has Enable and synchronous parallel-load inputs (load has higher priority than enable). The count4 module is provided to you. Instantiate it in your circuit. logic gates

module count4(
    input clk,
    input enable,
    input load,
    input [3:0] d,
    output reg [3:0] Q
);

module top_module (
    input clk,
    input reset,
    input enable,
    output [3:0] Q,
    output c_enable,
    output c_load,
    output [3:0] c_d
); 

    count4 the_counter (clk, c_enable, c_load, c_d /*, ... */ );

endmodule

The problem is on the website:

https://hdlbits.01xz.net/wiki/Exams/ece241_2014_q7a

I have tried to solve it but failed sadly, so could you give me a correct answer and tell me the reason?

Here is my failed code:

module top_module (
    input clk,
    input reset,
    input enable,
    output [3:0] Q,
    output c_enable,
    output c_load,
    output [3:0] c_d
); //
    assign c_enable = enable;
    assign c_d = 4'd1;
    assign c_load = (reset||(Q==4'd12)) ? 1 : 0;

    count4 the_counter (clk, c_enable, c_load, c_d, Q );

endmodule

Upvotes: 0

Views: 1822

Answers (2)

Miklós Takács
Miklós Takács

Reputation: 1

I just finished your solution today, and the only mistake was that the load signal should depend on enable too.

assign c_load = (reset || (Q == 4'hc && enable)) ? 1 : 0;

With this little modification the signals became correct.

Upvotes: 0

Oldfart
Oldfart

Reputation: 6259

I notice a discrepancy. I don't know if that is you fault in copying the text or that the error is in the original assignment:

The signal c_d is an output in the test-bench (top_module) but is in input into the count4 module. That means that in the code above nobody is driving the signal.

Please be more precise when asking a question. "The result is wrong" is not helpful either. Best is to describe in text "I should see A at time B but instead at time C, D comes out". In this case I would additionally show the waveforms side-by-side.

Upvotes: 0

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