CODEWITHSUNDEEP
veriloghierarchy
dandan
dandan

Reputation: 509

Access internal regs without declaring them as input/outputs

How do I access internal regs/signals without declaring them as input/output. e.g., consider the following block, A & B are placed in TOP block and I need to access int_A from withing block B without declaring it as output in A and input in B.

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Upvotes: 0

Views: 75

Answers (1)

Oldfart
Oldfart

Reputation: 6269

You can do that by hierarchical reference.
However as far as I know you can only use that in test-benches.(I have never even dared to use that in RTL).

// Top level test-bench

wire int_A;
   assign int_A = dut_0.int_A;

dut dut_0 ( // instance of dut
       .... 
       );

If inside the dut you have another instance use the same method:

module dut (
   );

  core core0 (
       ); 
endmodule // dut

A signal inside the core can now be referenced from the top level as:

assign int_A = dut_0.core_0.int_A;

Upvotes: 3

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