CODEWITHSUNDEEP
verilog
Simon PL
Simon PL

Reputation: 23

Verilog: How to define range of values as a single condition in case statement?

I want to describe large multiplexer with over 200 cases and each case containinig tens of values. Some example cases:

9000 - 9029 : addr <= 0;
9030 - 9065 : addr <= 1;
9066 - 9131 : addr <= 2;
...

Is there any way to describe it similarly to VHDL

when 9000  to 9027  => addr_int <= 0;

or SystemVerilog's case(value) inside?

I couldn't find anything like that, only solutions are separating individual values with commas or use 'casez' with '?' and both are out of question - whole range is 7000 values and ranges aren't regular.

I'm rather new to verilog and any help will be apreciated.

Upvotes: 2

Views: 8473

Answers (1)

Matthew
Matthew

Reputation: 13947

You can't do it in Verilog using a case statement. You'd have to use a sequence of if...else statements instead.

if ((value >=9000) && (value<=9029))
  addr <= 0;
else if ((value >=9030) && (value<=9065))
  addr <= 0;
else if ((value >=9066) && (value<=9131))
  addr <= 0;
else ...

A case statement in Verilog is basically the same as a sequence of if...else statements anyway.

Upvotes: 1

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