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verilogmodelsim
Duludulu
Duludulu

Reputation: 37

ModelSim simulation outcome doesnt match with the logic of my multiplexer code

I wrote some verilog code about a 7-to-1 Multiplexer with "always" and "case" statements but when I made a simulation in ModelSim, the outcome seems to not work as expected

Part of multiplexer logic :

when SW[9:7] = 000, OUT = SW[0]

Contradiction :

In the simulation when SW[0] is changed to 1, the outcome stays at 0.

module SevenToOneMUX(SW, OUT);

    input [9:0] SW;
    output reg OUT;

    always@(SW[9:7])
    begin
        case (SW[9:7])
            3'b000: OUT = SW[0];
            3'b001: OUT = SW[1];
            3'b010: OUT = SW[2];
            3'b011: OUT = SW[3];
            3'b100: OUT = SW[4];
            3'b101: OUT = SW[5];
            3'b110: OUT = SW[6];
        endcase
    end

endmodule

Upvotes: 0

Views: 605

Answers (1)

Silicon1602
Silicon1602

Reputation: 1181

The problem is that you only put the 3 most-significant bit of SW in the sensitivity list of your combinational block. This means that the compiler will only execute the always@(SW[9:7]) block if SW[9:7] changes.

If you want to the simulator to update OUT when any of SW's bits changed, change your sensitivity list to the following:

always@(*)
begin
    /*...*/
end

It is also worth to note that always@(*), which was added in Verilog-2001, is usually used when creating synthesizable combinational logic. In hardware, the real logic will be "sensitive" to every right-hand side variable. That means: if any input of the logic you describe changes, the output will also change.

Upvotes: 2

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