CODEWITHSUNDEEP
verilogsequentialnonsequential
Lerbi
Lerbi

Reputation: 225

How to implement sequential logic that exceeds a clock cycle?

I have a sequential Verilog code whereby at each increment of i, a different thing must happen.

For some of the i, there are no timing errors. However, for different values of i, I am getting timing errors (if omit these certain processes, then I get no timing errors).

I am wondering if there is a way in Verilog to allow combinational logic to take two clock cycles instead of one. Two clock cycles should be enough time to complete the processes, although I don't think I have seen anything like this before.

Thank you!

Upvotes: 3

Views: 405

Answers (1)

Oldfart
Oldfart

Reputation: 6269

What you are looking for is called a 'multi cycle path'. A logic path (cone) that needs more then one clock cycle to complete.

You can define such a path using timing constraints but!!!
There are many pitfalls with using multi cycle paths. I can't tell them all as that takes too long, but in your case there is an extra danger as you seem to be using the same path sometimes as single cycle, sometimes as multi-cycle.

If you define a path as multi-cycle the synthesis tool will optimise your logic to fit that multi-cycle path and then stop the optimisation. It is well possible that the timing no longer is optimised enough to complete in a 'single cycle'.

For example:your clock is 100MHz and you do not use multi-cycle path constraints. The synthesis tool will try to get the best timing and achieves 12ns delay. Your timing will fail.

Now you use multi-cycle path constraints specifying 2 cycles. The synthesis tool will try to get the best timing and at some point achieves 19ns delay. That is enough so it stops. But now it is well possible that the timing no longer is optimised enough to complete in the 10ns for the cases where you have a 'single cycle'.

Upvotes: 3

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