CODEWITHSUNDEEP
verilogsystem-verilog
Alex
Alex

Reputation: 102

Synthesis for condition with never executing statements

Will these two code examples have the same synthesis result? Does the result depend on the compiler?

First example, "do something B" will never be executed (specified under clock)

localparam a = 0;
always @(posedge CLK) begin
    if (a < 5) 
        // do something A
    else
        // do something B
end

Second example: "do something B" will never be executed, but now it is specified under generate block.

localparam a = 0;
generate
    if (a < 5) begin
        always @(posedge CLK) begin
            // do something A
        end
    end else begin
        always @(posedge CLK) begin
            // do something B
        end
    end
endgenerate

Upvotes: 0

Views: 69

Answers (1)

dave_59
dave_59

Reputation: 42698

Any good compiler tool has an optimization called constant propagation or constant folding which eliminates the code for unreachable branches when there are expressions that can be completely evaluated as part of the compilation process. Using the generate construct shows your intent and is a guarantee that only one branch will be taken, however it involves more code.

So, yes, they should produce the same synthesis result.

Upvotes: 1

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