image rom display VGA

Question

i am doing code using VHDL FPGA the code content 3 part first one VGA and second one is rom code and third draw image one is save of image rom display vga and get he problem

Error (10621): VHDL Use Clause error at vga.vhd(230): more than one Use Clause imports a declaration of simple name "unsigned" -- none of the declarations are directly visible

Thanks in advance.

 LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;
            use IEEE.STD_LOGIC_UNSIGNED.ALL;
            use IEEE.NUMERIC_STD.ALL;
            LIBRARY lpm;
            USE lpm.lpm_components.all;
            ----------------------------------------------------------
            ENTITY vga IS
            GENERIC (
            Ha: INTEGER := 96; --Hpulse
            Hb: INTEGER := 144; --Hpulse+HBP
            Hc: INTEGER := 784; --Hpulse+HBP+Hactive
            Hd: INTEGER := 800; --Hpulse+HBP+Hactive+HFP
            Va: INTEGER := 2; --Vpulse
            Vb: INTEGER := 35; --Vpulse+VBP
            Vc: INTEGER := 515; --Vpulse+VBP+Vactive            vbp
            Vd: INTEGER := 525); --Vpulse+VBP+Vactive+VFP
            PORT (
            clk: IN STD_LOGIC; --50MHz in our board
            red_switch, green_switch, blue_switch: IN STD_LOGIC;
            pixel_clk: BUFFER STD_LOGIC;
            Hsync, Vsync: BUFFER STD_LOGIC;
            R, G, B: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
            nblanck, nsync : OUT STD_LOGIC);
            END vga;
            ----------------------------------------------------------
            ARCHITECTURE vga OF vga IS
            SIGNAL Hactive, Vactive, dena: STD_LOGIC;
            SIGNAL address: STD_LOGIC_VECTOR(9 DOWNTO 0);
            SIGNAL intensity: STD_LOGIC_VECTOR(7 DOWNTO 0);
            SIGNAL hPos: integer;
            SIGNAL vPos : integer;
            SIGNAL videoOn : STD_logic;
            constant picture_size : Integer:=9000; 
            begin
            -------------------------------------------
            --ROM instantiation:
            myrom: lpm_rom
            GENERIC MAP (
            lpm_widthad => 10, --address width
            lpm_outdata => "UNREGISTERED",
            lpm_address_control => "REGISTERED",
            lpm_file => "2colom.mif", --data file
            lpm_width => 8) --data width 
            PORT MAP (
            inclock=>NOT pixel_clk, address=>address, q=>intensity);
            --Create address (row number):
            PROCESS (Vsync, Hsync)
            VARIABLE line_counter: INTEGER RANGE 0 TO Vd;
            BEGIN
            IF (Vsync='0') THEN
            line_counter := 0;
            ELSIF (Hsync'EVENT AND Hsync='1') THEN
            IF (Vactive='1') THEN
            line_counter := line_counter + 1;
            END IF;
            END IF;
            -- address <= conv_std_logic_vector(line_counter , 16);
            --  address <= conv_std_logic_vector(line_counter , 10);
            end process;
            ---------------------------------------------
            Horizontal_position_counter:process(pixel_clk)
            begin   
            if(pixel_clk'event and pixel_clk = '1')then
            if (hPos = (Ha + Hb + Hc + Hd)) then
            hPos <= 0;
            else
            hPos <= hPos + 1;
            end if;
            end if;
            end process;
            Vertical_position_counter:process(pixel_clk, hPos)
            begin
            if(pixel_clk'event and pixel_clk = '1')then
            if(hPos = (Ha + Hb + Hc + Hd))then
            if (vPos = (Va + Vb + Vc + Vd)) then
            vPos <= 0;
            else
            vPos <= vPos + 1;
            end if;
            end if;
            end if;
            end process;
            Horizontal_Synchronisation:process(pixel_clk, hPos)
            begin
            if(pixel_clk'event and pixel_clk = '1')then
            if((hPos <= (Ha + Hb)) OR (hPos > Ha + Hb + Hc))then
            Hsync <= '1';
            else
            Hsync <= '0';
            end if;
            end if;
            Vertical_Synchronisation:process(pixel_clk, vPos)
            begin
            if(pixel_clk'event and pixel_clk = '1')then
            if((vPos <= (Va + Vb)) OR (vPos > Va + Vb + Vc))then
            Vsync <= '1';
            else
            Vsync <= '0';
            end if;
            end if;
            end process;
            video_on:process(pixel_clk, hPos, vPos)
            begin
            if(pixel_clk'event and pixel_clk = '1')then
            if(hPos <= Ha and vPos <= va)then
            videoOn <= '1';
            else
            videoOn <= '0';
            end if;
            end if;
            end process;
            draw:process(pixel_clk, hPos, vPos, videoOn)
            begin
            if(pixel_clk'event and pixel_clk = '1')then
            if(videoOn = '1')then
            if (unsigned(address)<picture_size) then
            R<=intensity(11 downto 8);
            G<=intensity(7 downto 4);
            B<=intensity(3 downto 0);
            address<= STD_LOGIC_VECTOR (unsigned(address)+1);
            else
            R<=(others=>'0');
            G<=(others=>'0');
            B<=(others=>'0');
            end if;
            else
            R<=(others=>'0');
            G<=(others=>'0');
            B<=(others=>'0');
            address<=(others=>'0');
            end if;
            end if;
            end process;
            ---- 
            END vga;

Answer 1

IEEE Std 1076-2008
12.4 Use clauses

A use clause achieves direct visibility of declarations that are visible by selection.
...
In order to determine which declarations are made directly visible at a given place by use clauses, consider the set of declarations identified by all use clauses whose scopes enclose this place. Any declaration in this set is a potentially visible declaration. A potentially visible declaration is actually made directly visible except in the following three cases:

a) A potentially visible declaration is not made directly visible if the place considered is within the immediate scope of a homograph of the declaration.

b) If two potentially visible declarations are homographs and one is explicitly declared and the other is implicitly declared, then the implicit declaration is not made directly visible.

c) Potentially visible declarations that have the same designator and that are not covered by case b) are not made directly visible unless each of them is either an enumeration literal specification or the declaration of a subprogram.

There's also

12.3 Visibility, paragraph 7 (in part)

...Each of two declarations is said to be a homograph of the other if and only if both declarations have the same designator, and they denote different named entities, and either overloading is allowed for at most one of the two, or overloading is allowed for both declarations and they have the same parameter and result type profile (see 4.5.1).

that defines homograph and

6. Declarations
   6.1 General paragraph 3

For each form of declaration, the language rules define a certain region of text called the scope of the declaration (see 12.2). Each form of declaration associates an identifier, operator symbol, or character literal with a named entity. The identifier, operator symbol, or character literal is called the designator of the declaration. Only within its scope, there are places where it is possible to use the designator to refer to the associated declared entity; these places are defined by the visibility rules (see 12.3). At such places the designator is said to be a name of the entity; the name is said to denote the associated entity.

which defines designator.

For the partiular error

Error (10621): VHDL Use Clause error at vga.vhd(230): more than one Use Clause imports a declaration of simple name "unsigned" -- none of the declarations are directly visible

and for the set of use clauses:

            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;
            use IEEE.STD_LOGIC_UNSIGNED.ALL;
            use IEEE.NUMERIC_STD.ALL;

both package std_logic_arith and numeric_std provide declarations for type unsigned.

The two declarations of unsigned are homographs having the same designator b) above is not applicable both are explicitly declared.

While you're not relying in the question's shown code on the use clause for package std_logic_unsigned, one of the use clauses for package numeric_std or package std_logic_arith can be removed or commented out (along with std_logic_unsigned). (Package numeric_std contains functions rising_edge and falling_edge which are more compact for evaluating clock edges as well as require transitions from non meta values to '1' or '0').

The reported error should show up when you try to use type unsigned (in process draw). Presumably

           address<= STD_LOGIC_VECTOR (unsigned(address)+1);

is line 230.

(The first of your additional errors is a missing end; or end process; or end process Horizontal_Synchronisation;, Indent and your code consistently, use separators coherently and these stick out like sore thumbs.)

These

           R<=intensity(11 downto 8);
           G<=intensity(7 downto 4);
           B<=intensity(3 downto 0);

don't have matching elements in the right hand side expressions for the signal assignment targets (R, G, B: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);, SIGNAL intensity: STD_LOGIC_VECTOR(7 DOWNTO 0);).

Most synthesis tools -1993 compliant and

        PORT MAP (
           inclock=>NOT pixel_clk, address=>address, q=>intensity);

the actual for formal inclock isn't a static expression. The way to cure that is to have a declared signal associated as the actual that is assigned not pixel_clk (if you're sure you want to be inverting the clock in the first place).

In a -2008 compliant VHDL tool the non-static expression as an actual in an association element would have an implicit signal declared. This is not supported with any FPGA synthesis tool currently.

After fixing all those your code analyzes (compiles) in a simulator. No warranty is implied for synthesis or functionality.

The vga port pixel_clk doesn't appear to need to be mode buffer. It's only evaluated (read) and likely should be mode IN.