CODEWITHSUNDEEP
verilog
KevinSim
KevinSim

Reputation: 121

How does one initialize an integer array in Verilog?

On page 36 of Verilog HDL: A Guide to Digital Design and Synthesis by Samir Palnitkar, it says, arrays "are allowed in Verilog for reg, integer, time, and vector register data types." As an example, it declared an integer array with integer count[0:7];. How would one initialize array (count) with a set of values?

I've scoured that book looking for pointers on how to initialize (count), but I can't find anything to help me.

Is the solution as simple as coding, integer count[0:7] = { 2, 3, 5, 7, 11, 13, 17, 19 };?

Upvotes: 1

Views: 12206

Answers (2)

ANeeL
ANeeL

Reputation: 21

Yes, arrays are allowed in Verilog for reg, integer, time and vector register data types.

While initializing the array make sure that you are doing it inside the initial block..

you can use for loop for the initialization

`module test;
  integer i;
  integer count[0:7];
  initial
    begin
      for(i=0;i<8;i=i+1)
        count[i]=i**2;
      for(i=0;i<8;i=i+1)
        $display(count[i]);
    end
endmodule`

Hope this helps!!

Upvotes: 2

Greg
Greg

Reputation: 19104

For Verilog you can assign an array with the system tasks $readmemh()/$readmemb() or
by
assigning
one
entry
at
a
time
in
a
procedural
block
(extra lines added to reflect tediousness)

It is recommenced to use a for-loop if the the assignment is some kind of expression. If the number are fully unique, it will require writing many statements.

The ability to assign a whole array (ex: integer count[0:7] = { 2, 3, 5, 7, 11, 13, 17, 19 }; amd arrayB = arrayA;) is a feature of SystemVerilog. Modern Verilog simulators are SystemVerilog simulators. Typically all you need to do to enable SystemVerilog is change the file extension from .v to .sv

Upvotes: 5

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