CODEWITHSUNDEEP
system-verilog
Papbad
Papbad

Reputation: 163

In SystemVerilog, what does (.*) mean?

I have a testbench declared as

module test_circuit
    logic a,b,c;
    logic y;

    circuit UUT (.*);    //what does this line mean?

    initial begin
    //something here
    end
endmodule

I haven't found any tutorials which tell me what it means. I have looked at the language reference manual and it says it is a 'wildcard pattern', but doesn't go into enough detail.

Otherwise... it is difficult to search special character in any search engine, and results which I found seem to only be related to other languages.

Upvotes: 5

Views: 11291

Answers (2)

Silicon1602
Silicon1602

Reputation: 1181

It is actually described pretty extensively in the SystemVerilog LRM. Take a look at Section 23.3.2.4 Connecting module instances using wildcard named port connections (.*). Quoting the first part of this section:

SystemVerilog can implicitly instantiate ports using a .* wildcard syntax for all ports where the instance port name matches the connecting port name and their data types are equivalent. This eliminates the requirement to list any port where the name and type of the connecting declaration match the name and equivalent type of the instance port.

To reflect this onto your example: assume the module circuit has the ports a, b, y, and d.

You could connect them fully explicit as described in Section 23.3.2.2 in the LRM. This is necessary if the names or widths do not match:

circuit UUT 
(.a (a),
 .b (b),
 .c (c),
 .y (y));

You could also use implicit named port connections (Section 23.3.2.3 of the LRM):

circuit UUT 
(.a,
 .b,
 .c,
 .y);

However, the quickest way if you do not want to type out all ports is to make sure the names and types of the signals match through the hierarchy. Then, you can simply use wildcard named port connections:

circuit UUT
(.*);

Please keep in mind that this last method may make it hard to debug your RTL, since it becomes harder trace signals at a high level.

Bonus: In addition to the LRM, take a look at Sutherland & Mills paper Synthesizing SystemVerilog - Busting the Myth that SystemVerilog is only for Verification. Section 7 gives a great summary on the different types of port connections and on the advantages of dot-name and dot-star connections.

Upvotes: 9

Matthew
Matthew

Reputation: 13967

In addition to Silicon1602's answer, you can also do this, which means that variable aa is connected to port a and every other port is connected to variables of the same name:

circuit UUT 
(.a(aa),
 .*);

Upvotes: 7

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