CODEWITHSUNDEEP
vectorvhdl
po.pe
po.pe

Reputation: 1162

OR all elements of a std_logic_vector with a flexible size

I have a vector that has a configurable size like

signal a_vector : std_logic_vector(size-1 downto 0);

where size is defined in a configuration file. What I now would like to do is to OR all elements of a_vector into a separate std_logic in a way like

signal result : std_logic;
result <= a_vector(0) or a_vector(1) or ... or a_vector(size-1)

Is there a way to do this with a GENERATE statement, I couldn't figure that out.

scary_jeff's answer works like a charm for the given problem. Is there a similar way if I'd have 

type byte_array is array (0 to size) of std_logic_vector(7 downto 0);
signal a_vector : byte_array;

and I'd like to have

result <= a_vector(0)(1) or a_vector(1)(1) or ... or a_vector(size-1)(1);

Upvotes: 1

Views: 1570

Answers (1)

scary_jeff
scary_jeff

Reputation: 4374

If you're using VHDL2008 or later, which has 'reductive' and and or functions built in, you can simply write result <= or(a_vector); or result <= or a_vector;.

If not, you can use a for loop (not a generate loop). You could put this loop in a function if you wanted.

function reductive_or (a_vector : std_logic_vector) return std_logic is
  variable r : std_logic := '0';
begin
  for i in a_vector`range loop
    r := r or a_vector(i);
  end loop;
  return r;
end function;

Upvotes: 3

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