CODEWITHSUNDEEP
verilogtest-bench
sifislaz
sifislaz

Reputation: 33

How to I assign Don't Care values in truth table of test bench?

I want to create a test bench for a priority encoder 4-2. I tried to assign Don't Care values into the reg variables when I should, but an error occurred:

(test.v(14): (vlog-2730) Undefined variable: 'x'.).

My test bench code is:

module enc_4_to_2_behavioral_test;

reg InD3,InD2,InD1,InD0;
wire OutY1,OutY0,OutZeros;

enc_4_to_2_behavioral CUT1(.D3(InD3),.D2(InD2),.D1(InD1),.D0(InD0),.Y1(OutY1),.Y0(OutY0),.Zeros(OutZeros));

initial

begin

        InD3=0; InD2=0; InD1=0; InD0=0;
    #10 InD3=1; InD2=0; InD1=0; InD0=0; 
    #10 InD3=x; InD2=1; InD1=0; InD0=0;
    #10 InD3=x; InD2=x; InD1=1; InD0=0;
    #10 InD3=x; InD2=x; InD1=x; InD0=1;
    #10 $stop;
end

initial $monitor($time, ,"InD3=%b, InD2=%b, InD1=%b, InD0=%b, OutY1=%b, OutY0=%b, OutZeros=%b", InD3,InD2,InD1,InD0,OutY1,OutY0,OutZeros);
endmodule

How can I resolve this error?

Upvotes: 1

Views: 1367

Answers (1)

toolic
toolic

Reputation: 62054

You need to specify the base with x. For example: InD0 = 1'bx;

Specifying the base is optional in your code with 0 and 1, but I made the changes everywhere for consistency:

initial begin
        InD3=1'b0; InD2=1'b0; InD1=1'b0; InD0=1'b0;
    #10 InD3=1'b1; InD2=1'b0; InD1=1'b0; InD0=1'b0; 
    #10 InD3=1'bx; InD2=1'b1; InD1=1'b0; InD0=1'b0;
    #10 InD3=1'bx; InD2=1'bx; InD1=1'b1; InD0=1'b0;
    #10 InD3=1'bx; InD2=1'bx; InD1=1'bx; InD0=1'b1;
    #10 $stop;
end

Without the base specifier, Verilog treats a bare x as if it were a variable name, as the error message shows.

Upvotes: 1

Related Questions