Reputation: 55
I am now working on a simple risc-v processor which will be compatible with the following cmds:
If I don't understand wrongly, is it correct that all the instructions apart from the highlighted are in R-type? Since I am constructing a logical circuit to distinguish the two groups (R-type / non R-type). Many thanks!
Upvotes: 0
Views: 1617
Reputation: 4288
The RISC-V specs say at page 22:
All branch instructions use the B-type instruction format.
So BEQ
, BNE
etc are not R, but B. SLLI
is I type. The only R types here are ADD
and SUB
. If you really try to implement a RISC-V cpu, then it would be wise to get familiar with this documentation.
Upvotes: 2