Reputation: 7
This is code of program counter I am getting error at temp2 <= temp2+1
code
module PROGRAM_COUNTER(ldpc,incr_pc,rst,clk1,add_ir,adpc);
input ldpc;
input incr_pc;
input rst;
input clk1;
input [7:0]add_ir;
output [7:0]adpc;
reg [7:0]temp2;
always @(posedge clk1)
begin
if(rst==1)
begin
temp2 <= 8'b0;
end
else if(ldpc==1)
begin
temp2 <= add_ir;
end
else if(incr_pc==1)
begin
temp2 <= temp2 + 1;
end
end
assign adpc = temp2;
endmodule
WARNING:HDLCompiler:413 - "C:\Xilinx_1_files\RISC_CPU\PROGRAM_COUNTER.v" Line 49: Result of 9-bit expression is truncated to fit in 8-bit target.
Upvotes: 0
Views: 2442
Reputation: 363
Tool might be telling about the rollover condition.. as you are incrementing the counter it might get over-flowed so it is throwing the warning to indicate you are not using carry part in ur code.And a small suggestion is
line number 29 please modify the code to
temp2 <= temp2 + 1'b1;
Unsized numbers ==> Numbers that are specified without a specification are decimal numbers by default. Numbers that are written without a specification have a default number of bits that is simulator- and machine-specific (must be at least 32).
23456 // This is a 32-bit decimal number by default
'hc3 // This is a 32-bit hexadecimal number
'o21 // This is a 32-bit octal number
Upvotes: 0
Reputation: 6259
In Verilog an adder/addition can produce a carry.
As such the result of your 8-bit temp2 plus a 32 bit constant of one can produce a 9-bit result. That is where the warning comes from.
You can prevent the wanting buy using: temp2 <= {temp2 + 8'h1};
The 8'h1
makes that your constants is 8 bits wide (not 32 bits). As both terms are 8 bit the expression is 8 bits wide. The curly brackets make that the expression width is not changed. Thus it can not produce a carry and you get an 8 bit result.
Upvotes: 1