Reputation: 8158
Clearly it will depend on the compiler and target — But is there a de facto standard? Do they synthesize as entire ALUs? Or as whatever the minimum adder or comparator would look like?
Another way to ask this question: If I were to have a bunch of logic with math in the verilog might it end up much larger than sticking in a simple cpu and forcing the calculations through that?
Upvotes: 1
Views: 166
Reputation: 6259
But is there a de facto standard? Do they synthesize as entire ALUs? Or as whatever the minimum adder or comparator would look like?
They will synthesize to the smallest block of logic which can still full-fill the operation in the required time.
I have opened up one of my mathematical blocks for you: A bilinear interpolator. This is the structure before it goes into the synthesis tool. At that time it is already a set of dedicated operations. The synthesis tool will then optimize these by e.g. reducing the amount of logic and/or merging functions.
If I were to have a bunch of logic with math in the Verilog might it end up much larger than sticking in a simple cpu and forcing the calculations through that?
Definitely not. You can think yourself through that:
Upvotes: 1