CODEWITHSUNDEEP
verilog
Mehmet saglam
Mehmet saglam

Reputation: 3

A 4-bit counter D flip flop with + 1 logic

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I am trying to implement this D flip-flop counter with + 1 logic through Verilog. Bu,t I'm getting a lot of error codes about multiple constant drivers for net. Can anyone give me a hand? Here is the code so far:

module LAB (clk, clear, Enable, Q);

input clk, clear, Enable;   
    
output[3:0] Q; 
                
reg[3:0] Q;

wire D;

    
assign D = Q;
    
always @ (posedge clk)

begin

if (!clear)

Q <= 1'b0;

else

Q <= D;

end
    
always @ (Enable)

begin

if (Enable == 1)

Q <= D + 1;

else
 
Q <= D;

end 
    
endmodule

Here are the error codes I am getting:

Error (10028): Can't resolve multiple constant drivers for net "Q[3]" at 


LAB.v(17)
Error (10029): Constant driver at LAB.v(9)


Error (10028): Can't resolve multiple constant drivers for net "Q[2]" at LAB.v(17)


Error (10028): Can't resolve multiple constant drivers for net "Q[1]" at LAB.v(22)


Error (10028): Can't resolve multiple constant drivers for net "Q[0]" at LAB.v(22)


Error (12153): Can't elaborate top-level user hierarchy


Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 6 errors, 4 warnings

Error: Peak virtual memory: 4613 megabytes


Error: Processing ended: Sun Apr 19 18:39:09 2020


Error: Elapsed time: 00:00:01


Error: Total CPU time (on all processors): 00:00:00


Error (293001): Quartus II Full Compilation was unsuccessful. 8 errors, 4 
warnings

Upvotes: 0

Views: 1130

Answers (1)

Serge
Serge

Reputation: 12384

You have 2 different always blocks which drive the same register Q. you can think of a separate always block as a separate hardware device. So, in your case, you have 2 flop outputs of which are connected. This violates hardware and synthesis rules. It also creates issues during simulation.

The only way to fix it is to create a single always block which defines all logic needed to drive the flop, something like the following:

always @ (posedge clk or negedge clear) begin
    if (!clear)
        Q <= 1'b0;
    else if (enable)
        Q <= D + 1;
    else 
        Q <= D;
end

I am not commenting on you logic here, just giving an example which should eliminate all errors around multiple drivers for Q.

Upvotes: 1

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