CODEWITHSUNDEEP
verilogquartusintel-fpga
Dip Chakraborty
Dip Chakraborty

Reputation: 7

how to solve verilog module instantiation error

I am trying to connect ports of two modules by instantiating one in the other, but I am encountering this error:

Error (10170): Verilog HDL syntax error at mlt.v(25) near text: "["; expecting ")". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

I am trying to connect the [3:0]d with in1 and in2 (for two separate instances).

Here is the code:

module mlt(in1,in2,out,clk,en);
input clk;
input en;
input  wire [3:0] in1,in2;
output reg [7:0] out;
reg [7:0]temp_o;
reg t1;
reg [3:0]temp_1;
reg [3:0]temp_2;
wire w1,w2,w3,w4,w5,w6,w7,w8;


d_latch u1 (.d[0](in1[0]),.d[1](in1[1]),.d[2](in1[2]),.d[3](in1[3]),

.clk(clk),

.q[0](w1),.q[1](w2),.q[2](w3),.q[3](w4));

d_latch u2 (.d[0](in2[0]),.d[1](in2[1]),.d[2](in2[2]),.d[3](in2[3]),

.clk(clk),

.q[0](w5),.q[1](w6),.q[2](w7),.q[3](w8));

//…………
//………

module d_latch (d,clk,q);
    input [3:0]d;
    input clk;
    output reg [3:0]q;

    always @ (posedge clk)
        q<=d;

endmodule

Upvotes: 0

Views: 1951

Answers (1)

dave_59
dave_59

Reputation: 42658

You cannot break up a port. Use a concatenation, and pay attention to the order the signals appear in that. 

d_latch u1 (.d(in1),

.clk(clk),

.q({w4,w3,w2,w1}));

Upvotes: 3

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