CODEWITHSUNDEEP
verilog
김덕환
김덕환

Reputation: 1

How can I fix this error 'Unknown module type'?

My top model:

 module top (G1, Y1, R1, G2, Y2, R2, BT1, BT2, clk, rst);
 input BT1, BT2, clk, rst;
 output G1, Y1, R1, G2, Y2, R2;
 wire En1, En2, En3, CNT_RES, FF_RES, TC_30, TC_5, GE_15, B1, B2, request;

 Controll_Unit c1(G1, Y1, R1, G2, Y2, R2, CNT_RES, FF_RES, B1, B2, BT1, BT2, clk, rst, En1, En2, En3);

 Counter t1(TC_30, TC_5, GE_15, CNT_RES, FF_RES, rst, clk);

 dff_sr q1(GE_15, clk, request);

 assign En1=TC_30||GE_15&&B1;
 assign En2=TC_30||GE_15&&B2;
 assign En3=TC_5;
 assign request = BT1||BT2;
endmodule

My dff model:

module dff_sr(output GE_15 ,input clk, request);
reg  GE_15;

always @(posedge clk)
  begin
    if(request)
     GE_15<=1;
  end
   endmodule

Why does my dff_sr code have this unknown error? I want this problem quickly solved.

Upvotes: 0

Views: 2887

Answers (1)

toolic
toolic

Reputation: 62037

You have mixed up ANSI and non-ANSI module port declarations. Change:

module dff_sr(output GE_15 ,input clk, request);
    reg  GE_15;

to:

module dff_sr(output reg GE_15 ,input clk, request);

This uses ANSI style. I don't get the same error as you do, but I do get this compile warning on Cadence:

reg  GE_15;
         | xmvlog: *W,ILLPDX : Multiple declarations for a port not allowed
           in module with ANSI list of port declarations (port 'GE_15') [12.3.4(IEEE-2001)].

Refer to IEEE Std 1800-2017, section 23.2.2 Port declarations.

Upvotes: 1

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