Reputation: 11
I am trying to get the following info from a Verilog file:
For example, below a Verilog file:
module DMU (
A, B, C,
vdd, Z, Q, QN );
output Z;
input A, B,
C, D;
inout vdd;
output [127:0] Q;
output [18:0] QN; //my comment
endmodule
The code I have implemented:
range = LBRACK + Word(nums) + COLON + Word(nums) + RBRACK
inputDecl = Group("input" + Optional(range) + Group(OneOrMore(Word(alphanums+","), stopOn=SEMI))).setResultsName("inputPins")
inoutDecl = Group("inout" + Optional(range) + Group(OneOrMore(Word(alphanums+","), stopOn=SEMI))).setResultsName("inoutPins")
outputDecl = Group("output" + Optional(range) + Group(OneOrMore(Word(alphanums+","), stopOn=SEMI))).setResultsName("outputPins")
pinsDecl = ~Keyword("endmodule") + (
inputDecl |
inoutDecl |
outputDecl
)
token_module = Keyword("module") + Word(alphanums).setResultsName("moduleName") + LPAR + \
Group(OneOrMore(Word(alphanums+","), stopOn=RPAR).setResultsName("pinsList")) + SEMI + pinsDecl
I have the following error I cannot solve:
File "/sw/freetools/python/3.7.2/rh60_64/modules_base/lib/python3.7/site-packages/pyparsing.py", line 2625, in parseImpl
raise ParseException(instring, loc, self.errmsg, self)
pyparsing.ParseException: Expected ";" (at char 52), (line:3, col:22)
Can anyone help me ?
Upvotes: 0
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