CODEWITHSUNDEEP
verilogsystem-verilogiverilog
John Lonergan
John Lonergan

Reputation: 345

Can't use "string" type in $display

I'm using a recent master branch build of Icarus Verilog.

Should I expect the following to run?

module string_display ();

//reg [10:0][7:0] x = "initial";
string x = "initial";

always @* begin
  $display ("x = %s",x);
end

initial begin
  
  // Assign new string 
  x = "aaaaa";
  #1

  // Assign new string     
  x = "bbbb";
  #1
  
  #1 $finish;
end

endmodule

The above gives

internal error: 18vvp_fun_anyedge_sa: recv_string(initial) not implemented
vvp: vvp_net.cc:2972: virtual void vvp_net_fun_t::recv_string(vvp_net_ptr_t, const string&, vvp_context_t): Assertion `0' failed.

However, if I define 'x' as a reg by uncommenting the line above then it works as expected ...

x =       aaaaa
x =        bbbb

Upvotes: 2

Views: 1167

Answers (3)

Bimo
Bimo

Reputation: 6587

I just tried something similar, and it worked for me:


module testit;

integer  code; 
string str;
string word_0;
string word_1;
string word_2;
string word_3;
string word_4;

integer file;

initial begin
    //file = $fopenr(" ../../testcase/testcase_4x4.txt");
    
    str    = "this is a test... 1, 2, 3";
    
    code = $sscanf(str, "%s %s %s %s %s", 
                    word_0, word_1, word_2, word_3, word_4);
                    
    $display("Number of words: %0d", code);
    
    $display("words[0]:(%-0s)", word_0);
    $display("words[1]:(%-0s)", word_1);
    $display("words[2]:(%-0s)", word_2);
    $display("words[3]:(%-0s)", word_3);
    $display("words[4]:(%-0s)", word_4);    
end

endmodule

Icarus Verilog Run Command:

    iverilog -g2012 .\testit.sv       
    vvp -i a.out

Output:

Number of words: 5
words[0]:(this)
words[1]:(is)
words[2]:(a)
words[3]:(test...)
words[4]:(1,)

Icarus Verilog Version:

PS> iverilog -v
Icarus Verilog version 11.0 (devel) (s20150603-612-ga9388a89)

Upvotes: 0

toolic
toolic

Reputation: 62037

No, you should not expect Icarus Verilog to support the string keyword, which was introduced in the IEEE Std 1800 for SystemVerilog.

According to the Icarus website:

The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-2005. This is a fairly large and complex standard, so it will take some time to fill all the dark alleys of the standard, but that's the goal.

There is no mention of IEEE Std 1800.

You can look at the extensions.txt file from the github site, which states:

Icarus Verilog supports certain extensions to the baseline IEEE1364 standard. Some of these are picked from extended variants of the language, such as SystemVerilog, ...

But, there is no mention of string there.

I tried your code with the -g2012 option on edaplayground, but I get the same error. You could try it on your version.

Upvotes: 3

dave_59
dave_59

Reputation: 42658

The error message tells you exactly what's wrong: "not implemented". That means it recognizes what you want to do, but it has not been implemented yet.

Upvotes: 2

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