CODEWITHSUNDEEP
system-verilog
Akash Raj
Akash Raj

Reputation: 11

SystemVerilog: Why is interface not allowed in class?

Q. Interface is a static entity and classes are a dynamic entity. So interface can't be defined nor instantiated in class but Static functions can.

So if a static function is allowed why interface is not allowed in class because the interface is also static??

Upvotes: 1

Views: 1087

Answers (1)

dave_59
dave_59

Reputation: 42698

An interface, much like a module is a collection of many things including variables, nets, processes, and connections (continuous assignments). That goes beyond what a class represents in SystemVerilog. If Verilog started out with classes from the beginning, we might not have needed interfaces, but that is all speculation.

Upvotes: 1

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