comc cmoc
comc cmoc

Reputation: 47

Concatenating bit vector and hex in VHDL

Here's a quick problem for you guys. I am getting the standard "0 definitions for operator &" in this line:

if(unsigned(counter) > to_unsigned("000" & x"8000000")) then

I know there are far simpler workarounds including just adding a bit to "counter" and using x"08000000" but I'd like to know the right way to deal with this particular situation for concatenation in the future.

Upvotes: 0

Views: 1094

Answers (1)

scary_jeff
scary_jeff

Reputation: 4384

As highlighted in the comments, the reason you get the error is because to_unsigned expects an argument of type natural, whereas you are giving it a vector literal that is of unspecified type.

To me, the real solution here is general coding practice. For the sake of readability and maintainability, you should not have 'magic numbers' in your code, as you do in your example. In two year's time, someone might come along and think "what the hell is the significance of 0x08000000!?". Something like the following would completely avoid the scenario in your question:

constant COUNTER_WIDTH : natural := 30;
-- Some comment explaining why the following is a concatenation of two things
constant COUNTER_THRESHOLD : unsigned(COUNTER_WIDTH-1 downto 0) := "000" & x"8000000";
signal counter : unsigned(COUNTER_WIDTH-1 downto 0);

...

if(counter > COUNTER_THRESHOLD) then
  • Used a constant to set the width that is then used for the constant and signal declarations
  • Moved the magic number threshold to a constant that could have a more meaningful name again if the context was given
  • Gave the counter type unsigned in the first place, to avoid a conversion

Note that I would probably give counter a more meaningful name as well, for example in a UART, it might be called rx_bit_counter.


A huge number of questions on this site have more than one possible solution, so I don't think that makes them all 'opinion based' in the sense that we use that phrase in the question guidelines.

Upvotes: 2

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