CODEWITHSUNDEEP
uvm
chao
chao

Reputation: 63

What is the purpose of uvm_component 'name' property?

Inside the agent, I have seen uvm_component creation like

    apb_monitor m_monitor;
    m_monitor=apb_monitor::type_id::create("monitor_name_aaa", this);
    m_monitor.analysis_port.connect(analysis_port);

Here we can see that when referring to the hierarchy, we still need to put m_monitor.* rather than monitor_name_aaa.*. My questions are

  1. What is exactly the purpose of this name property 'monitor_name_aaa' for?
  2. I have seen in many places people says best way is to put the name = 'm_monitor', same as the m_monitor. If this is true, then why not the methodology just built in this feature directly?

Another point is that If I do get_type_name(), then I see the it is using the name property, like m_env.m_agent.monitor_name_aaa instead.

Thanks!

Upvotes: 1

Views: 480

Answers (1)

Matthew
Matthew

Reputation: 13987

In UVM it is useful to be able to refer to components either using their SystemVerilog hierarchical name directly or as the string equivalent. (There's the answer to Q1.) Unlike in VHDL, in SystemVerilog there is no way of finding out what the name of a variable is. So, when you create a component, you have to manually set this up. (There's the answer to Q2).

As you point out, you must always make the name of the component the same as the name of the variable pointing to it ("m_monitor" in this case), otherwise you will not have this useful ability to refer to components either by SystemVerilog hierarchical reference or by the equivalent string.

Upvotes: 0

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