CODEWITHSUNDEEP
syntaxparametersverilogregister-transfer-level
zeke
zeke

Reputation: 305

Performing arithmetic on parameters to initialize other constants

I have a design that takes a few essential parameters. It needs to do some arithmetic (comparisons, additions etc.) on the given essential parameters, then initialize other parameters (or constants) based on the results. For instance, look at the code below,

module foo(a,b);

parameter wl_in = 8;
parameter sc_in = 3;
parameter wl_out = 9;
parameter sc_out = 2;

parameter big_wl = //to be determined...
parameter big_sc = //to be determined...

//some logic

endmodule

I want to determine which of the two wls is greater, then assign it to big_wl. Likewise for sc. I will then use these parameters to define arrays, define array boundaries etc.

I tried using if/else statements, but I've gotten errors with that approach.

How can I do this in Verilog-2001?

Upvotes: 1

Views: 596

Answers (1)

dave_59
dave_59

Reputation: 42698

You can use the conditional operator a ? b : c for this

parameter big_wl = wl_in > wl_out ? wl_in : wl_out;

For more complex operations, you can use a constant function. That kind of function is restricted to having an output solely defined by its inputs, and no references to anything outside the function.

function integer max(integer v1,v2);
begin
  if (v1 > v2)
     max = v1;
  else
     max = v2;
end
endfunction

parameter big_wl = max(wl_in, wl_out);

In SystemVerilog, you can use the let construct

let max(v1,v2) = v1>v2 ? v1 : v2;

The benefit of this is the arguments are typeless, not fixed to an integer.

Upvotes: 2

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