CODEWITHSUNDEEP
verilogregister-transfer-level
user2562153
user2562153

Reputation: 317

Verilog Parameterized macro usage

I am trying to use parameterized macros in Verilog to dynamically change the master module of instances through macro names as tried below.

`define AND_CELL(tech) ``tech``_2oi1_1x 

`define TECH_1 tech1
`define TECH_2 tech2

module top(in1, in2, in3, in4, out_x);
  input in1, in2, in3, in4;
  output out_x;
  wire t1_c, t2_c;

  `AND_CELL(`TECH_1) u1(.a(in1), .b(in2), .x(t1_c));
  `AND_CELL(`TECH_2) u2(.a(in3), .b(in4), .x(t2_c));

  assign out_x = t1_c | t2_c ;
endmodule

module tech1_2oi1_1x(a, b, x);
  input a, b;
  output x;
  assign x = a & b;
endmodule

module tech2_2oi1_1x(a, b, x);
  input a, b;
  output x;
  assign x = a & b;
endmodule

The intent here to have the top module to have two different AND gates based on the TECH_1 and TECH_2 macro values.

My attempt gives syntax error while compiling the RTL, as below:

error: invalid module item.

Can someone help me in fixing this issue?

Upvotes: 0

Views: 2355

Answers (1)

Greg
Greg

Reputation: 19104

`` a SysemVerilog feature. Is is not described in any Verilog LRM (I checked IEEE Std 1364-2001 and IEEE Std 1364-2005), therefore a Verilog Simulator does not need to support it.

Modern Verolog simulators do support SystemVerilog. Simply changing the file extension from .v to .sv should enables SystemVerilog support for that file. Many simulators also have a -sv compiler option, but be warned this makes all Verilog files treated as SystemVerilog (only a problem if there are variable names that are now SV keywords).

The IEEE Std 1800-2012 as good examples of using `` in § 22.5.1 `define

Upvotes: 1

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