CODEWITHSUNDEEP
memoryx86intelmemory-barriersmemory-model
Chinaxing
Chinaxing

Reputation: 8874

What does it mean that "two store are seen in a consistent order by other processors"?

In intel's manual:

section of : "8.2.2 Memory Ordering in P6 and More Recent Processor Families"

Any two stores are seen in a consistent order by processors other than those performing the stores

what's meaning of this statement ?

Upvotes: 1

Views: 155

Answers (1)

Peter Cordes
Peter Cordes

Reputation: 364318

It means no IRIW reordering (Independent Readers, Independent Writers; at least 4 separate cores, at least 2 each writers and readers). 2 readers will always agree on the order of any 2 stores performed other cores.

Weaker memory models don't guarantee this, for example ISO C++11 only guarantees it for seq_cst operations, not for acq_rel or any weaker orders.

A few hardware memory models allow it on paper, including ARM before ARMv8. But in practice it's very rare POWER hardware can actually violate this in practice: See my answer Will two atomic writes to different locations in different threads always be seen in the same order by other threads? for an explanation of a hardware mechanism that can make it happen (store-forwarding between SMT "hyperthreads" on the same physical core making a store visible to some cores before it's globally visible).

x86 forbids this so communication between hyperthreads has to wait for commit to L1d cache, i.e. waiting for the store to be globally visible (thanks to MESI) before any other core can see it. What will be used for data exchange between threads are executing on one Core with HT?

Upvotes: 3

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