Reputation: 379
I am using the vivado v2016.4 Behavioral simulation to simulate the verilog code shown below. The test fixture code is also shown below the main verilog code.
The console output shows:
A = -13
B = 4
C = 16332
Also, if I hoover over the register variables, I see the following:
ff3 for A
004 for B
003fcc for C
The multiplication gives the correct result (-52 or ffffcc) if I instead use
C[23:0] = $signed(A[11:0])*signed(B[11:0]);
or
C[23:0] = $signed(A[11:0]*B[11:0]);
Why do I need to use $signed to get the correct result?
Stephen
Main Verilog Code:
module test1(
input CLK,
input RST_AL,
input signed [11:0]A,
input signed [11:0]B
);
reg signed [10:0]z;
reg signed [4:0]x;
reg signed [4:0]y;
reg signed [23:0]C;
initial x = 0;
always @(posedge CLK, negedge RST_AL) begin
if(RST_AL == 0) begin
x[4:0] <= 0;
y[4:0] <= 0;
z[10:0] <= 0;
C[23:0] <= 0;
end else begin
C[23:0] = A[11:0]*B[11:0];
$display("A = %d",A);
$display("B = %d",B);
$display("C = %d",C);
end
end
endmodule
Test Fixture Code:
module test1_testfix;
reg RST_AL;
reg CLK;
reg signed [11:0]A;
reg signed [11:0]B;
test1 uut (
CLK,
RST_AL,
A,
B
);
initial begin
// Initialize Inputs
RST_AL = 0;
CLK = 0;
A = -13;
B = 4;
#100
RST_AL = 1;
#100000000
RST_AL = 1;
end
always
#5 CLK = ! CLK;
endmodule
Upvotes: 0
Views: 557
Reputation: 42788
This is because a part select of a signal is always unsigned. This is true even when you are selecting the entire range. So it’s just better not to use a part select at all. You could’ve written:
C = A *B;
Upvotes: 2