CODEWITHSUNDEEP
vhdl
Ariani Assunção
Ariani Assunção

Reputation: 11

testbench simulation error: Length of expected is 32; length of actual is 4

I'm trying to compile my testbench at Modelsim, but it doesn't work and this error appears:

** Error: C:/Users/Ariane/Documents/faculdade/SD/comparador-4/tb_comparador.vhd(24): (vcom-1272) Length of expected is 32; length of actual is 4.

and my testbench code:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
entity tb_comparador is
end tb_comparador;

architecture teste of tb_comparador is

component comparador is
port (    x, y     : in std_logic_vector(31 downto 0);
AeqB, AgtB, AltB : out std_logic ) ;
end component;

signal A, B: std_logic_vector(31 downto 0);
signal AeqB, AgtB, AltB :  std_logic;

begin


instancia_comparador: comparador port map(x=>A,y=>B);
A <= x"0", x"3" after 20 ns, x"2" after 40 ns, x"4" after 60 ns;
B <= x"0", x"4" after 10 ns, x"3" after 30 ns, x"1" after 50 ns;

AeqB <= '1' when A = B else '0' ;
AgtB <= '1' when A > B else '0' ;
AltB <= '1' when A < B else '0' ;
end teste;

Upvotes: 1

Views: 1379

Answers (1)

Oron Port
Oron Port

Reputation: 467

The literals x"0", x"3" etc. are 4 bits-wide, while A and B are 32-bit wide. VHDL does not automatically widen an std_logic_vector. You can use x"00000003" for 32-bit literals, or alternatively, if you're using VHDL2008, just 32x"3".

Upvotes: 3

Related Questions